EE180 Digital System Architecture

Winter 2021, Tue/Thu 1:30PM-3PM
Location: Shriram Ctr 104

Instructor: Christos Kozyrakis
Teaching Assistant: Timothy Chong, Sneha Pendharkar, Sam Xu
Ed Discussion: Ed Stem
Gradescope Entry Code: KYWVRP
Canvas: Cavnas Home Page
Course Information: PDF

EE180 introduces students to computer architecture and the design of efficient computing and memory systems. The key topics of this course include: hardware/software interface (instruction set, data and thread level parallelism), assembly language programming, efficiency metrics (performance, power, energy, and cost), processor design (pipelining and vectors), memory hierarchy (cache, main memory), virtualization, basic I/O, and custom accelerator design. The programming assignments provide an introduction to performance optimization of software on a modern architecture and the design of a processor.
  At the completion of the course, you will understand how to determine the performance of processor-based digital systems, why they are designed that way, and how to implement your own accelerator design.
  EE180 is appropriate for undergraduate and graduate students who are specializing in the interrelated discipline of hardware/software systems. It is also appropriate for other EE and CS students who want to understand, optimize, or design their own processor based digital-system of any scale in their day-to-day work. Post EE180, students can take EE282, a class on advanced computer system architecture, and modern datacenter hardware/software architecture.

Schedule

Required Textbook:
H&P: J. Hennessy & D. Patterson, Computer Organization & Design: The Hardware/Software Interface, 5th edition, Morgan-Kaufmann, 2013.
The book is available at the Stanford Bookstore, and an unlimited-use eBook is available via the Terman Engineering Library . The book is also available in print or digital form by online retailers.

DateTopicReading AssignmentClass Info
1/4 Introduction H&P: 1.{1-5}
1/6 Hardware/Software Interface I H&P: 2.{1-4, 6}
1/11 Hardware/Software Interface II
H&P: 2.{7-10}
1/13 Hardware/Software Interface III H&P: 2.{4, 11-14}
H&P: 6.3
1/18 Efficiency Metrics
H&P: 1.{6-7}
1/20 Hardware Design Overview
H&P: Appendix B
1/25 Processor Design H&P: 4.{1-4}
1/27 Pipelined Processor I H&P: 4.{5-6}
2/1 Pipelined Processor II
H&P: 4.7
2/3 Pipelined Processor III
H&P: 4.{8-10}
2/8 Memory Hierarchy I H&P: 5.{1-4}
2/10 Midterm Exam
2/15 Memory Hierarchy II H&P: 5.{5-6}
2/17 Memory Hierarchy III
H&P: 5.{8-10}
2/22 Custom Accelerators
Lectrue Notes
2/24 Virtual Memory

H&P: 5.7
3/1 Operating System Support
H&P: 4.9
3/3 I/O Devices & Interfaces
H&P: 6.9
3/8 I/O optimizations
Lecture notes
3/10 Advanced architectures & Security Lecture notes
3/15 Final Exam (3:30PM - 6:30PM)

Homework and Projects

We recommend you to work on all assignments in groups of 2 students. All problem sets are due by 11:59pm PDT on the dates indicated on the assignment. Solutions to homework sets will be available online shortly thereafter. All deadlines are final. No extensions, no exceptions. Late assignments will not be accepted. All assignments should be submitted through GradeScope.

Tentative schedule:
  • Problem Set 1: release 1/20, due 2/3
  • Problem Set 2: release 2/3, due 2/17
  • Problem Set 3: release 2/22, due 3/3
  • Lab 1: release 1/11, due 1/18
  • Lab 2: release 1/18, due 2/1
  • Lab 3: release 2/1, due 2/22
  • Lab 4: release 2/22, due 3/8

Logistics

Announcements: Visit this web page regularly to access all the handouts, solutions, and announcements.

Office Hours:
Monday: Sam 4:00PM-5:30PM
Wednesday: Tim 10:00AM-11:30AM
Friday: Sneha 2PM-3:30PM
Location: Packard B52

Online Quiz: The midterm exam will be an 1.5-hour open-book quiz. It will be available to take online for a period of 24 hours (you will choose the 1.5 hours that work best for you).

Final Exam: The final exam will be held in person (assuming COVID constraints allow us to). The exact arrangements will be announced towards the end of the quarter.

Tentative Grading scheme:
Homework: 15%
Class participation : 10%
Lab Assignments: 35%
Midterm exam: 20%
Final exam: 20%

Collaboration: See: honor code and collaboration for some general guidelines, which apply to both project assignments and problem sets. In general, collaboration is encouraged subject to the following guidelines:

Adapted from a template by Andreas Viklund.