MIPS-Light Instruction Set Summary

The MIPS-Light ISA is a stripped down version of the MIPS R2000 ISA which is very close to the DLX ISA that is described in the textbook. The main difference between MIPS-Light ISA and DLX ISA concerns the branch instructions. MIPS-Light allows branches that have equal and not-equal comparisons between any two registers. When one of the registers is r0, the branch instruction is equivalent to a beqz or a bnez instruction in DLX. Please ignore references to the instructions BLTZAL and BGEZAL, which are not implemented in the MIPS-Lite Verilog model.

5.0.1 Instruction Formats

In addition to the standard R2000 formats shown above, the MIPS-lite instruction set also has an additional format for the bltz and bgez instructions:

Bit:		[31-26]		[25-21]		[20-16]		[15-0]
Field:		op=REGIMM	rs		sub		offset

5.0.2 Load and Store Instructions

5.0.3 ALU Instructions

5.0.4 Jump and Branch Instructions

ERRATA: The correct JALR instruction format is:

	JALR rd, rs