Computer Systems Laboratory Colloquium

4:15PM, Wednesday, May 6, 1998
NEC Auditorium, Gates Computer Science Building B03

Academic Computer Architecture Research Refocussed
New Challenges, New Technology, and Old Architectures

David A. Patterson
University of California, Berkeley
About the talk:

For two decades architecture research has been focussed on desktop or server machines. As a result of that attention, today's microprocessors are 1000 times faster than original Berkeley RISC and Stanford MIPS chips. Given the looming consolidation of desktop microprocessor architectures, it may be time to declare victory and look for new research challenges.

One candidate is personal mobile computing, where portable devices are used for visual computing and personal communications tasks. Such a device supports in an integrated fashion all the functionalities provided by a portable computer, a cellular phone, a digital camera and a video game today. In addition, we believe speech I/O will be the cornerstone of such devices.

This new challenge brings new demands for architects. This application cares much more about real-time performance than the performance target of today's out-of-order microprocessors (average case performance or SPEC performance). These programs typically operate on vectors of 8-bit or 16-bit samples of audio and visual data and 32-bit floating point data, not the 64-bit data of today's machines. In addition to high performance for multimedia and DSP functions, requirements include energy efficiency and area efficient, scalable designs.

As a starting point, we propose reviving vector architectures. Vector architectures match the narrower widths and real-time demands of multimedia. They also scale well with increasing number of transistors and wire-delay challenges of future integrated circuits. Unlike conventional DSPs, they have a foundation of compiler research which allows them to be programmed in high-level languages. And unlike the MMX-style instruction set extensions, vector arhcitectures have an elegant and fast interface to memory and scale well with vector length.

A vector machine benefits from a low-latency, high bandwidth memory. Intelligent RAM, or IRAM, merges processing and memory into a single chip to lower memory latency, increase memory bandwidth, improve energy efficiency, and reduce size. Hence IRAM appears to be an excellent technology for mobile computing. Surprisingly, the integration of the processor/cache/memory of IRAM with with high-speed serial I/O lines may also lead to very good I/O performance.

I conclude by describing the design of VIRAM-1, a microprocessor designed by graduate students that may well have more transistors than the contemporary Intel microprocessor. The goal is that in 2-3 years VIRAM-1 will consume less than 2 watts of power, contain 16-32 MBytes of memory, have about 1 GByte/sec of I/O, and crunches at the rate of 1-2 GFLOPS (64-bit floating point) and 4-16 GOPS (16-bit fixed point). It may also challenge DSP performance even though programmed in high-level programming languages.

The repercussions of success extend beyond the architecture research community. Today's semiconductor industry is sharply divided into processor and memory camps. If IRAM proves successful, unification may come to the semiconductor industry. In such a future, its unclear which company will ship the most processors.

(To follow the IRAM Project , see /

About the speaker:

DAVID A. PATTERSON (University of California at Berkeley) has taught computer architecture since joining the faculty in 1977, and is holder of the E.H. and M.E. Pardee Chair of Computer Science. He is a member of the National Academy of Engineering, is a Fellow of the Computer Society of the Institute of Electrical and Electronic Engineers (IEEE), and is also a Fellow of the the Association for Computing Machinery (ACM). His teaching has been honored by the ACM with the Karl V. Karlstrom Outstanding Educator Award, by IEEE with the Undergraduate Teaching Award, by the University of California with the Distinguished Teaching Award, and by his department with the Diane S. McEntyre Award for Excellence in Teachin g. He received the inaugural Outstanding Alumnus Award of the UCLA Computer Science Department as part of its 25th Anniversary and in 1995 he received the IEEE Technical Achie vement Award.

He is past chair of the CS Division in the EECS department at Berkeley, the ACM Special Interest Group in Computer Architecture, and the Computing Research Association. He has consulted for many companies, including Digital, Hewlett Packard, Intel, and Sun Microsystems, and is also co-author of five books (including two with John Hennessy.)

At Berkeley, he led the design and implementation of RISC I, likely the first VLSI Reduced Instruction Set Computer. This research became the foundation of the SPARC architecture, currently used by Fujitsu, Sun Microsystems, and Xerox. (In 1996 Microprocessor Report and COMDEX named SPARC as one of the significant microprocessors as part of the celebration of the 25th anniversary of the microprocessor.) He was also a leader of the Redundant Arrays of Inexpensive Disks (RAID) project, which led to high performance storage systems from many companies. These projects led to three distinguished dissertation awards from the ACM. His current research interests are in large-scale computing using networks of workstations (NOW) and in building novel microprocessors using Intelligent DRAM (IRAM).

Contact information:

David A. Patterson
Computer Science Division, 390 Soda Hall #1776
University of California
Berkeley, California 94720-1776