The AMULET group at the University of Manchester has spent a decade researching the application of asynchronous design techniques to low power processor cores and system-on-chip applications. The latest processor core, AMULET3, is a 100 MIPS ARM9-class machine that supports the ARM instruction set, including the Thumb 16-bit compressed ISA. It employs architectural techniques not yet seen in clocked ARM cores, such as a branch target buffer and a reorder buffer, where architectural choices are strongly influenced by the asynchronous pipeline operation.
AMULET3 is about to enter commercial use as a component on the DRACO telecommunication controller, which also incorporates the MARBLE asynchronous on-chip bus and a complex 32-channel DMA controller developed using the Balsa asynchronous logic synthesis tool.
In this talk I will describe the principles of asynchronous design used in the development of AMULET3 and discuss the rationale for the processor's organisation. I will also describe the main features of the DRACO chip and the advantages gained from the use of an asynchronous processing subsystem.
About the speaker:
Steve Furber is the ICL Professor of Computer Engineering in the Department of Computer Science at the University of Manchester. He received his B.A. degree in Mathematics in 1974 and his Ph.D. in Aerodynamics in 1980 from the University of Cambridge, England. From 1980 to 1990 he worked in the hardware development group within the R&D department at Acorn Computers Ltd, and was a principal designer of the BBC Microcomputer and the ARM 32-bit RISC microprocessor, both of which earned Acorn Computers a Queen's Award for Technology. Since moving to the University of Manchester in 1990 he has established the AMULET research group which has interests in asynchronous logic design and power-efficient computing. He is a Fellow of the Royal Academy of Engineering and the British Computer Society, a Chartered Engineer, and a Member of the IEEE.
Department of Computer Science
The University of Manchester
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