Current microprocessor industry trends towards optimizing single-thread performance will, if continued, lead to exceedingly complex cores that are unlikely to perform well for commercial workloads. These applications are known to yield poor instruction-level parallelism, although they are rich in thread-level parallelism.
In this talk I will review our group's research on understanding the behavior of commercial workloads, and describe the architecture that it inspired: Piranha. Piranha is a research prototype that uses chip-multiprocessing as the basis for a scalable shared memory system that is optimized for database and web/internet server workloads. The project is a partnership between Compaq Research and the Compaq NonStop Hardware Division.
About the speaker:
Luiz André Barroso has been a member of the research staff at the Compaq Western Research Lab since 1995 (when it was still Digital). His current interests are in computer architecture and design of server-class systems, cache coherence protocols, and commercial workload performance. He holds a PhD in Computer Engineering from USC, and MS/BS degrees in Electrical Engineering from PUC University, Rio de Janeiro.
Luiz André Barroso
Compaq Western Research Laboratory
250 University Ave.
Palo Alto, CA 94301