A brief overview of present and future CMOS process variations will be presented. Prevailing understanding of a chip's behavior under large process variations with statistical delay assumptions leads one to conclude that a small number of errors are likely as we progress further down on Moore's Law. This understanding is challenged by a new hypothesis on the behavior of very large CMOS chips in the presence of process variations. A Thought Experiment is presented which leads to the new hypothesis. The new hypothesis states that in every large CMOS chip, there exist critical operations points (frequency, voltage, temperature) such that it divides the 3-D space (F, V, T) in to two distinct spaces: 1. Error-free operation and 2. Massive errors (i.e. completely inoperable). Two attempts at disproving this hypothesis with real physical experiments will be described. More rigorous experiments to either prove or disprove this hypothesis are suggested. Some consequences of the hypothesis on power saving and aging are also suggested.
Key words: Circuit Design, Statistical Design, Process Variations, Functional Testing, Speed-binning, dynamic-voltage-frequency management
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About the speaker:
Janak H. Patel is Donald Biggar Willet Professor of Engineering and Co-Director of Center for Reliable and High-Performance Computing at the University of Illinois at Urbana-Champaign. He also holds the position of Professor in Departments of Electrical and Computer Engineering and Computer Science.
Patel's research contributions include Pipeline Scheduling, Cache Coherence, Cache Simulation, Multiprocessor memory modeling and analysis, Interconnection Networks, On-line Error Detection, Reliability analysis of memories with ECC and scrubbing, Design for Testability, Built-In Self-Test, Fault Simulation and Automatic Test Generation. Patel has supervised over 75 M.S. and Ph.D. theses and published over 200 technical papers.
Janak H. Patel