### Stanford EE Computer Systems Colloquium

##### 4:15PM, Wednesday, April 2, 2008

HP Auditorium, Gates Computer Science Building B01

http://ee380.stanford.edu

####
CMOS Process Variations:

A "Critical Operation Point" hypothesis

#####
Janak H. Patel

HP Laboratories and Stanford University (visiting)

On Sabbitical Leave from Univerity of Illinois

**About the talk:**
A brief overview of present and future CMOS process variations will be
presented. Prevailing understanding of a chip's behavior under large
process variations with statistical delay assumptions leads one to
conclude that a small number of errors are likely as we progress
further down on Moore's Law. This understanding is challenged by a new
hypothesis on the behavior of very large CMOS chips in the presence of
process variations. A Thought Experiment is presented which leads to
the new hypothesis. The new hypothesis states that in every large CMOS
chip, there exist critical operations points (frequency, voltage,
temperature) such that it divides the 3-D space (F, V, T) in to two
distinct spaces: 1. Error-free operation and 2. Massive errors (i.e.
completely inoperable). Two attempts at disproving this hypothesis
with real physical experiments will be described. More rigorous
experiments to either prove or disprove this hypothesis are suggested.
Some consequences of the hypothesis on power saving and aging are
also suggested.

Key words:
Circuit Design, Statistical Design, Process Variations, Functional
Testing, Speed-binning, dynamic-voltage-frequency management

**Slides:**

Download the slides for this presentation
in PDF format.

**About the speaker:**

Janak H. Patel is Donald Biggar Willet Professor of Engineering and
Co-Director of Center for Reliable and High-Performance Computing at
the University of Illinois at Urbana-Champaign. He also holds the
position of Professor in Departments of Electrical and Computer
Engineering and Computer Science.

Patel's research contributions include Pipeline Scheduling, Cache
Coherence, Cache Simulation, Multiprocessor memory modeling and
analysis, Interconnection Networks, On-line Error Detection,
Reliability analysis of memories with ECC and scrubbing, Design for
Testability, Built-In Self-Test, Fault Simulation and Automatic Test
Generation. Patel has supervised over 75 M.S. and Ph.D. theses and
published over 200 technical papers.

**Contact information:**

Janak H. Patel