About the talk:
Conventional memories such as SRAM, DRAM, and FLASH have set a very high cost/performance standard. Yet, recent advances in new materials, device technologies and circuits have made many emerging memories attractive candidates for a new generation of memories.
The worldwide research and development effort on emerging memory devices can be understood from two perspectives. From a system point of view, processor performance is increasingly limited by memory access and power consumption of the memory subsystem. Recent efforts in extending the scalability of SRAM and incorporating embedded DRAM in advanced technologies are evidence of the importance of the memory technology. The emergence of Flash as a solid-state complement and/or replacement of the hard disk drive for selected applications has highlighted the enormous potential of a high-density, embedded memory technology within the memory hierarchy. At the same time, memory device research has had a renaissance of new ideas. New memory devices, most of them non-volatile, have been explored and some have progressed beyond the observation of a hysteresis effect to device-level demonstrations. These new memory devices, such as STTRAM, PCM and RRAM, have read/write/retention/endurance characteristics different from conventional SRAM, DRAM, and Flash. The very high density offered by some of the new device technologies may also lead to the replacement of the hard disk drive (HDD) by solid-state devices for some applications.
There is an enormous opportunity to completely re-think the design of the memory subsystem to gain orders of magnitude improvements in speed and/or power consumption. A revolution in the memory subsystem will bring about a fundamental change in how one can extract performance out of technology improvements.
This talk gives an overview of emerging memory devices, drawing upon our recent research work on phase change memory (PCM) and metal oxide resistive switching memory (RRAM). We will examine the technical challenges for emerging non-volatile memory devices going forward including device physics and scaling properties, followed by suggestions for directions for future research.
Live Video Stream:
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About the speaker:
|H.-S. Philip Wong joined Stanford University as Professor of Electrical Engineering in September, 2004. From 1988 to 2004, he was with the IBM T.J. Watson Research Center. He held various positions from Research Staff Member to Manager, and Senior Manager. While he was Senior Manager, he had the responsibility of shaping and executing IBM's strategy on nanoscale science and technology as well as exploratory silicon devices and semiconductor technology. His present research covers a broad range of topics including carbon nanotubes, biosensors, self-assembly, exploratory logic devices, nanoelectromechanical relays, device modeling, and novel memory devices such as phase change memory and metal oxide resistance change memory. He is a Fellow of the IEEE and served on the Electron Devices Society AdCom as elected member (2001 -- 2006). He served as the Editor-in-Chief of the IEEE Transactions on Nanotechnology in 2005 -- 2006, sub-committee Chair of the ISSCC (2003 -- 2004), General Chair of the IEDM (2007), and is currently a member of the Executive Committee of the Symposia of VLSI Technology and Circuits (2007 -- 2010). He received the B.Sc. (Hons.), M.S., and Ph.D. from the University of Hong Kong, Stony Brook University, and Lehigh University, respectively. He currently holds the Chair of Excellence of the French Nanosciences Foundation.|
H.-S. Philip Wong
Professor of Electrical Engineering
Center for Integrated Systems
Room CISX 312
Stanford, CA 94305-4075
URL: URL: http://www.stanford.edu/~hspwong