EE410 : Integrated Circuit Fabrication Laboratory

Winter 2010-11, Prof. Krishna Saraswat


Contents


Announcements

The first organizational meeting of EE410 will take place on Wednesday, January 5, in Allen (formerly CIS) 101X at 12:00pm. In this meeting we will divide the class into groups. The Class size will be limited to 24 students (4 groups of 6 students each). You are expected to be available for one full morning or afternoon for the laboratory session during Tuesdays - Thursdays. There will be no lab sessions on Mondays or Fridays. If you miss this meeting your chances of taking the class will be diminished as the class size is limited to 24 students.

There will be about 6 one hour meetings through the quarter including the course organization meeting. Please bring your availability schedule with you to this meeting.

There will be a second meeting on Friday, January 8 at 12 pm in Allen 101X on safety in the Stanford Nanofabrication Facility (SNF) followed by a safety tour of the SNF. If you miss this meeting you won't be allowed to take the course unless you have taken the SNF safety class earlier. If you have already taken the SNF safety class send me the date you took it.

Before you take the lab safety tour you are required to view the video material online at your own leisure. There are three videos at: http://snf.stanford.edu/Access/LabClass.html. There is a manual at the same site. Read the manuals and take the safety test before the Friday tour (which are included in the training folders to be given to you in the first meeting). Videos, manual and test take about 3-4 hours to complete

Check your group assignment by clicking here after Thursday, January 6.


Course description

The course involves CMOS process simulation using SUPREM, laboratory fabrication, testing and characterization of silicon gate CMOS devices and simple integrated circuits. Emphasis is on the practical aspects of IC fabrication, including silicon wafer cleaning, photolithography, etching, oxidation, diffusion, ion implantation, chemical vapor deposition, physical sputtering and wafer testing. Specifically the course is diveded in three parts:
1. CMOS fabrication for silicon integrated circuits.

2. CMOS process simulation using SUPREM.

3. Device testing and characterization.

4 units for CMOS (3 units option is possible), Letter grade only.

Class size will be limited to 24 students divided into 4 groups. Each group will be led by a TA. Each group will meet once a week for an entire morning or afternoon. Preference will be given to those who are planning to use the IC Lab fabrication facility for their research.

Prerequisites:

EE212 and EE216 or equivalent required.

Text: None. Notes will be provided.

References:

EE212 text and notes, Plummer, Deal and Griffin.

VLSI Technology, Sze.

Silicon Processing for the VLSI Era, Vol. 1 & 2, Wolf & Tauber.

Atlas of IC Technologies, Maly

Semiconductor Material and Device Characterization, Schroder.

Pierret, "Semiconductor Device Fundamentals", Addison-Wesley.

Muller and Kamins, "Device Electronics for Integrated Circuits", Wiley.

Modern Semiconductor Devices for Integrated Circuits, Chenming Hu.


Class schedule

Lecture:

About 6 meetings will take place through the quarter.

1. "Course organization meeting" - 1/5/2011, Wednesday, 12:00 - 1:00 PM, Allen 101X.

2. "SNF Lab safety training tour" Friday, 1/7/2011, SNF.

View the video material online at your own leisure before the safety tour. There are three videos at: http://snf.stanford.edu/Access/LabClass.html.

There is a manual at the same site. Read the manuals and take the safety test before the Friday tour (which are included in the training folders). Students are encouraged to work together.

Videos, manual and test take about 3-4 hours to complete.

Take lab tours from 12-2 on Friday. Tours are about 1 hour long. We will have 2 tours. one at noon and the next at 1 pm.

3. "Cleaning and clean Processing Techniques" - 1/14/2011, Friday, 12:00 - 1:00 PM, Allen 101X

4. "Process simulation using TSUPREM" - 1/21/2011, Friday, 12:00 - 1:00 PM, Allen 101X

5. "Test structures in EE410 mask sets and Testing" - 2/18/2011, Friday, 12:00 - 1:00 PM, Allen 101X

6. "Comparison of EE410 CMOS process with industry standard processes" date and time TBD


Lab:

4 to 6 hours per week of laboratory work in one morning or afternoon on a weekday by arrangement.


Handouts

Electronic versions of some handouts will be available in Adobe's increasingly popular PDF format. Viewing and printing the handouts and assignments will require the use of Adobe's Acrobat Reader, the latest verison of which can be downloaded for FREE! from Adobe's Web Page. Click here to travel there. Additional course notes will be provided during the lectures.

Handout #1 on Introduction to EE410

Handout #2 Safety test

Handout #3 Acknowledgement

Handout #4 on on CMOS-LOCOS Manual

Handout #5 on EE410 CMOS Process

Handout #6 on Cleaning and Contamination

Handout #7 on Process Simulation

Handout #8 on Running TSUPREM on campus computers

Handout #9 on Test Structures and Testing

Handout #10 on Advances in MOS Technology


Teaching staff

Professor: Krishna Saraswat
Room: Allen 326X
Phone: (650) 725-3610
Office Hours:To be announced
Email: saraswat@cis.stanford.edu
Administrative Assitant: Gail Chun-Creech
Room: CISX 329
Phone: 723-0983
Email: CREECH@snow.stanford.edu
Teaching Assitants:
Group 1:
Email:
Group 2:
Email:
Group 3:
Email:
Group 4:
Email:

Grading

1. Lab Performance: 25%

As determined by your TA and the SNF staff.

2. Process and Device Modeling Paper: 25%

Each student will simulate the EE410 CMOS process and write a report. You may consult with other students in your group or in the class, however, the simulations and other calculations should be done by each student individually and the report is to be written also by each student individually.

CONTENT

Less than 10 pages of main body. It should be written similar to a paper published in a Journal. Any supporting material should go in an appendix.

SIMULATION

(by TSUPREM, etc.) and calculations of the structures (e.g. thickness, doping profile, ..........) and electrical parameters (e.g. sheet resistance, threshold voltage, ..........) that should result from the process flow. Organize the report in the following format.

I) Introduction

Include a short overview of the process and the structure

II) Analytical calculations (by hand)

a) Field and gate oxide thicknesses

b) Ion implant profiles

c) Junction depths

d) Sheet resistance of junctions and poly-Si gate

e) Threshold voltages

III) TSUPREM Simulations on the same topics as in II)

IV) Comparison and Discussion

A table showing SUPREM values and hand calculated values and a discussion on discrepancies.

V) Conclusion

VI) References

SCHEDULE

1 copy of the paper will be due on 2/7/2011

GRADING

The paper will be graded according to the following guidelines :

Completeness of information 10%

Quality of presentation 10%

Innovations and others 5%

3. Group Report: 50%

The lab report is to be written as a group report. It may be divided up into chapters and each chapter written by a designated member of the group. Please indicate on the report specific contributions of the individuals.

CONTENT:

The style of the report should be similar to a PhD thesis (but not as long). It should include at least the following chapters :

1. A discussion of the process flow used, including the reasons for each step, problems encountered and solutions adopted

2. Simulations (by SUPREM, PISCES, etc.) and calculations of the structures (e.g. thickness, doping profile ..........) and electrical parameters (e.g. sheet resistance, threshold voltage ..........) that should result from the process flow (Similar to the Process and Device Modeling Paper)

3. Methodology and results of measurements taken on test structures, devices and circuits

4. Comparison of (2) and (3) and explanations of all discrepancies

5. Conclusions and comments

SCHEDULE:

One copy of the final report will be due on Monday, 3/14/2011 (The report will be kept for record)

GRADING:

The paper will be graded according to the following guidelines :

Completeness of information 25%

Quality of presentation 20%

Innovations and others 5%

Check your grades by clicking here.