Ben Varkey Benjamin
As luck would have it, I got an offer from a VLSI services company, a job that introduced me to chip design, a field I would explore during my three years in the industry. I was exposed to various subdisciplines: front-end (RTL/gate) design, physical design, back-end (circuit/layout) design and so on. Among these, I was fascinated by analog and mixed-signal design, which I wanted to learn more about, and so I enrolled in graduate school at Stanford with this intention.
My current focus is on devising strategies for using deep submicron devices for neuromorphic designs, strategies that could be migrated to new devices as they become available. Analog computation is cheap in terms of power. However, in deep sub-micron processes, the design overhead to make traditional analog designs work in the face of leakage and mismatch is becoming prohibitive. We need a design framework that would ensure a working design in the face of issues like temperature dependence and mismatch. This framework will still be useful when newer devices with better electrostatic control than planar MOSFETs become available.
To expand the quadratic/cubic leaky integrate and fire (LIF) neuron's repertoire of behaviors, I designed a resonator neuron, which exhibits a Hopf bifurcation. As this design could also be configured to exhibit a saddle-node bifurcation, it realizes richer neuronal behavior while having almost the same footprint as the LIF neuron.
I also briefly worked on porting CMOS neuron designs to silicon nanowires. Then I worked on Neurogrid, testing, characterizing and calibrating the chips, while also helping with software development for interfacing Neurogrid with the PC. While working on Neurogrid, I came across a few issues that led me to my current focus.
Neurogrid uses PTAT biases (proportional to absolute temperature) to compensate for temperature. However, not all its circuits take advantage of this to display temperature invariant behaviors, which result in issues like temperature-dependent firing rates. Neurogrid uses minimalist circuits, which are clever but result in second order effects more visible in deep-submicron technologies. For instance, parasitic capacitors dump charge, which results in a fast transient that deviates from the designed time constant. There are also uncompensated diode drops that make the design less scalable with decreasing supply voltage. I am currently working on a systematic approach to low-power designs that will help minimize these issues and more.