Downloads: Silicon Compiler

ChipGen is a silicon compiler, written in-house, that facilitates building neuromorphic systems. Using it, you can compile a chip in minutes, starting with the layout of your neuromorphic circuit. This tool, implemented with Tanner Inc's L-Comp macros, arrays your layout, places transceiver circuitry around it (to multiplex or demultiplex spikes), and generates the pad-frame. You can download it here. To learn more about designing neuromorphic chips, check out About our Work.

Neuromorphic Chip Design with ChipGen Beginning with a metapixel layout, ChipGen creates a verified chip layout within minutes.

You use ChipGen by giving it a metapixel to tile to create a silicon-neuron array.

Silicon neurons, organized in rows and columns, are connected together using address-events (AER): Each silicon neuron is assigned an address that is encoded and communicated to other arrays when it spikes. The spike is recreated at the target by decoding this address, establishing a virtual connection, or softwire.

In its present incarnation, ChipGen uses word-serial address-events: The transmitter encodes all of a row's spikes in a single burst—the row's address followed by a column address for each spike. The receiver decodes this burst into a row-wide data-word that is written to the addressed row in parallel. Our lab continually upgrades ChipGen to incorporate the latest developments in AER communication.

ChipGen makes it easy to create neuromorphic systems that are both modular and scalable.
In addition to your neuromorphic circuit, which may be anything from a single spiking neuron to a complex arrangement of dendrites, somas, and excitatory and inhibitory synapses, your layout needs to include the standard AER interface. This digital circuitry activates the row- and column-request lines when your silicon neuron spikes and activates your synapse circuit when the row- and column-select lines are active. If your neuromorphic circuit has multiple neurons or synapses, just tell ChipGen to allocate multiple row/column-request/select lines to it—that's the metapixel concept.

After tiling your metapixel, ChipGen places and routes AER transceiver circuitry and the pad-frame. It compiles row/column arbiters, encoders and decoders automatically from a cell library (included), with the right number of inputs/outputs and the right pitch. The cell library is compatible with MOSIS SCN_DEEP (deep submicron) design rules and currently uses five metal layers.

Before submitting the compiled chip for fabrication, you can verify everything is correct by comparing the layout with a schematic generated by ChipGen. In addition to LVSing (layout versus schematic), we recommend you compile a small version of your chip—it only takes minutes after all!—and simulate it with SPICE. Read more about designing with ChipGen in our reference manual.

Our tools are distributed under the terms of the GNU Public License, with the following addendums:

  1. You are responsible for any use of these resources that infringe on existing patents. (We are not aware of any such existing IP.)

  2. Although we have built several functional chips using these tools, we offer no warranty that your chip will work.

  3. Any publications that result from using these tools must cite our relevant publications.

You are agreeing to these terms and conditions by downloading our tools:

Download ChipGen: Our toolkit, together with AER cell library, example metapixel layout, schematics, and simulation testbenches.

Download Reference Manual: Explains how to create and verify layout with ChipGen.

You will need Tanner Inc's L-Edit Pro layout editor (version 11.x or higher) to use our tools; it runs on a PC under Microsoft Windows.

If you want to include fixed or programmable biases on your chip, check out Tobi Delbruck's Bias Generator Design Kits.