From Murmann Mixed-Signal Group
received the B.Sc. and M.Sc. degrees from Ain Shams University, Cairo, Egypt in 2006 and 2010 respectively, and the PH.D. degree from Universite Pierre et Marie Curie, Sorbonne Universites, Paris, France in 2013, all in electrical engineering. From 2006 to 2009, he was an analog design engineer in Si-Ware Systems. From 2009, he joined LIP6/UPMC, where he worked on digitally assisted high speed ADCs. From 2014, he is a postdoctoral research fellow in Murmann Mixed-Signal Group at Stanford University, Stanford, CA.
- Circuit Design in FinFET Technology
For advanced technology nodes of few tens of nm's, the FinFET technology has been evolved as a way to overcome the challenges facing the conventional planar CMOS. In FinFET, the gate surrounds the vertical non-planar transistor channel, which gives the transistor more control on the conducting channel and helps minimizing the short channel effects of planar CMOS technology. The 3D structure of the FinFET, however, introduces new challenges, both in the frontend and the backend of the circuit design process. While the intrinsic gain of the device becomes significantly higher due to the gate 3D control, the vertical channel of the FET makes the associated parasitics more significant, decreasing the maximum transition frequency of the device. In the backend of the FinFET process, due to the complex processing steps, which stem from both the non-planar structure and the extremely small dimensions, the layout of the circuits is becoming more constrained, with a significant number of restricted design rules, and approaches a grid-like layouts.
This project investigates the challenges in the frontend and the backend of the FinFET. The advantage of this new process with the effect of its associated parasitics is being benchmarked by designing high speed AMS circuits, initially targeting SAR ADC. On the backend side, the project is aiming to explore the benefit of automating the layout of the circuits, especially with the added constraints in the design rules of the FinFET. With the significant parasitics and Layout-Dependent Effects (LDE) of the FinFET, the automatic layout generation in real time would benefit the designers to see the effect of the layout on their schematics, and thus minimizes the design cycle by diminishing the latency between schematic design and layout generation.