Kevin Zheng

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BSEE, Massachusetts Institute of Technology, 2012

MSEE, Massachusetts Institute of Technology, 2013

Email: kevzheng@stanford.edu

Research: Power Efficient Allocation of Analog Pre-filtering and Quantization in ADC Based High Speed Links

Modern serial link data speed has exceeded 25Gbps, and we are approaching the physical limitations of channel capacity at such high data rates for PAM2 signaling. As devices continues to scale , ADC based links gained much attention due to its ability to realize more sophicated equaliztion in digital domain and work with other modulation schemes such as PAM4 and duobinary to overcome current challenges. However, a moderate resolution (5-7 bits) ADC sampling at >20GS/s is power inefficient with today's CMOS technology [1].

My research focuses on system level analysis of ADC based links with analog pre-filtering/equalization to relax quantizer's design specification. Quantization error could be shown to have smaller effect to BER due to its bounded nature in Probability Distribution domain. Within this PDF framework, many of the ADC's non-idealities can also be considered, such as non-linearity and DNL. Using this simple approach, it could be shown that analog equalizer in front of the ADC could help relax the specification significantly (almost by 1 bit).


Besides, I am also exploring new power efficient analog equalizer and ADC architecture for link application. We are studying a Pade delay cell based filter to push most equalization to receiver side with several benefits. A subranging Flash ADC architecture is also proposed to save power while relax requirements on metastability. My research goal involves a silicon implementation of such a power efficient analog front end and show the effectiveness of the system level analysis performed.<span style="line-height: 1.5em;" />

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[1] B. Murmann, “Energy limits in A/D converters,” in 2013 IEEE Faible Tension Faible Consommation, 2013, pp. 1–4.

[2] J. Kim, E. H. Chen, J. Ren, B. S. Leibowitz, P. Satarzadeh, J. L. Zerbe, and C.-K. K. Yang, “Equalizer Design and Performance Trade-Offs in ADC-Based Serial Links,” IEEE Trans. Circuits Syst. I, vol. 58, no. 9, pp. 2096–2107, Sep. 2011.

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