From Murmann Mixed-Signal Group
BSEE, Iowa State University, 2008
MSEE, Iowa State University, 2009
Admitted to Ph.D. Candidacy: 2009-2010
Research: High Speed Analog Filters and Equalizers
As high-speed links push for higher and higher throughputs, the increasing baud rate and signal bandwidth make it challenging and costly to equalize entirely in digital domain. Because of this fact there are now opportunities to perform some of the equalization in the energy efficient analog domain. Recent publications (Momtaz et al., JSSC 2010) have implemented feed-forward equalizers (FFEs) but have relied heavily on area expensive inductors and high power circuits. In this project, we are building a FFE equalizer using only inverters and capacitors. It is highly efficient due to the class AB operation of the inverter transconductors. Also, there are a low number of parasitic nodes, which translates to high bandwidth with no need for inductive peaking. The design promises to be compatible with and to benefit from future process scaling.
To account for the process, voltage, and temperature variations, a novel switched capacitor master/slave biasing circuit has been designed and will be included in the chip to perform background calibration of the delay cells. The design will be fabricated in a TSMC40 process and will be state of the art in terms of power and noise performance, as well as area. It is a crucial step in the direction of making analog equalization realizable in future high-speed links.
Email: rboesch AT stanford DOT edu