# Bill Chen

### From Murmann Mixed-Signal Group

BASc, University of Toronto, Canada, 2010

MS, Stanford University, 2012

Admitted to Ph.D. Candidacy: 2010-2011

**Research**: *Digitally Assisted, High-Speed Sampling Circuits*

Constant demands in the higher performance of wideband spectrum analyzers and cellular base stations push for the design of high bandwidth and high linearity frontend ADCs. Critical components like the ADC driver and sample and hold circuit largely determine the achievable performance. Currently, BJT buffers and voltage-mode switched capacitor samplers using either analog or complicated digital linearization techniques are implemented in the state-of-the-art ADC parts.

In this project, we further leverage the powerful digital linearization capabilities offered by CMOS by designing a new class sampling circuits that are architected with digital correction abilities in mind; i.e. the analog circuit is optimized such that its nonlinear errors are “easily” removable in the digital domain.

The proposed architecture is the current integrating S/H first described in [1]. Unlike the traditional voltage-mode S/H, this circuit first converts the input voltage into current through a transconductor, and then integrates the current onto a capacitor for a fixed amount of time through a MOS switch to form the sampled output. Due to the nature of the signal through the sampling switch being a current, the nonlinear on-resistance will have much less effect on the sampler nonlinearity than the voltage-mode S/H. The nonlinearity of the transconductor now becomes the major source of contribution for S/H distortion. However, this distortion, in general, yields a simpler model and can be easily corrected digitally. Furthermore, the frontend transconductor also acts as a signal buffer, thus removing the need of a BJT driver for the ADC. As a result, the ADC can be fully integrated into an all CMOS backend DSP for a system on chip product.

[1] L. Carley and T. Mukherjee, “High-speed low-power integrating CMOS sample-and-hold amplifier architecture,” Proceedings CICC, Sept. 1995.

**Email**: [chenbill AT stanford DOT edu]