Bill Chen

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BASc, University of Toronto, Canada, 2010
MS, Stanford University, 2012
Admitted to Ph.D. Candidacy: 2010-2011

Research: Digitally Assisted, High-Speed Sampling Circuits

Constant demands for higher performance in wideband spectrum analyzers and cellular base stations push the design of high-bandwidth and high-linearity frontend ADCs. Critical components like the ADC input buffer and sample and hold circuit largely determine the achievable performance. Currently, BJT buffers and boot-strapped switch samplers [1] or entire BJT frontend [2] are implemented in the state-of-the-art ADC parts.

In this project, we want to leverage the powerful digital linearization capabilities offered by CMOS by modeling the frequency-dependent nonlinearity in the frontend sampler and inversely correct it in the digital domain obviating the need of an expensive BJT process. Our previous work has demonstrated this concept through modeling the simplified behavior of the NMOS switch sampler of a commercial ADC and linearizing the output in the digital domain with well-controlled foreground model calibration.

In the next step of this project, we proposed to develop a more comprehensive nonlinearity model covering not only the switch itself but also the frontend input buffer (source follower). With a more complex model, we need to further develop a more advanced digital adaptive filter using indirect training to take into account of the poles in the system model where previously there are only zeros.

Further more, we propose to automate the entire model parameter calibration process in the background by implementing an auxiliary conversion path. The auxiliary path includes a relatively slower and noisier, but linear sample-and-hold and ADC core circuits. This serves as the linearity reference signal for the main path. Due to the nature of the adaptive filter, random noise in the auxiliary path will not affect the correction procedure.


Our final goal in this project is to design a new sampler circuit and develop an optimal digital post-correction technique that demonstrates a substantial advancement in the product of linearity and bandwidth using CMOS technology.

[1] A. Ali, et al. , “A 16 b 250 MS/s IF-sampling pipelined A/D converter with background calibration,” in IEEE Journal Solid-State Circuits, Dec. 2010, pp. 2602-2612.

[2] R. Payne, et al. , “A 16-Bit 100 to 160 MS/s SiGe BiCMOS Pipelined ADC witch 100 dBFS SFDR,” in IEEE Journal Solid-State Circuits, Dec. 2010, pp. 2613-2622.

Email: [chenbill AT stanford DOT edu]

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