Kevin Zheng

From Murmann Mixed-Signal Group

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BSEE, Massachusetts Institute of Technology, 2012

MSEE, Massachusetts Institute of Technology, 2013

Email: kevzheng@stanford.edu

Research: Power Efficient Allocation of Analog Pre-filtering and Quantization in ADC Based High Speed Links

Modern serial link data speed has exceeded 25Gbps, and we are approaching the physical limitations of channel capacity at such high data rates for PAM2 signaling. As devices continues to scale , ADC based links gained much attention due to its ability to realize more sophicated equaliztion in digital domain and work with other modulation schemes such as PAM4 and duobinary to overcome current challenges. However, a moderate resolution (5-7 bits) ADC sampling at >20GS/s is power inefficient with today's CMOS technology [1].

My research focuses on system level analysis of ADC based links with analog pre-filtering/equalization to relax quantizer's design specification. In the scenario that perfect equalization (also very power inefficient) were achieved, only a 2 bit quantizer is needed with PAM4. An optimal exists in power/resource allocation between analog equalization and ADC for desired performance. New frameworks of analyzing ADC based links are also required since low resolution ADCs are non-linear [2]. My research also attempts to create an information-centric framework (BER, entropy, mutual information, etc.) combined with the conventional waveform-centric analysis (SNR, MSE, etc.) to provide new insights for defining specifications and design. I will also explore a new Pade delay cell based analog FFE to achieve better analog signal conditioning. Ultimately I aim to obtain an power efficiency optimal point for the whole system and implement/assemble a proof-of concept link transceiver to demonstrate the effectiveness of such links.

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[1] B. Murmann, “Energy limits in A/D converters,” in 2013 IEEE Faible Tension Faible Consommation, 2013, pp. 1–4.

[2] J. Kim, E. H. Chen, J. Ren, B. S. Leibowitz, P. Satarzadeh, J. L. Zerbe, and C.-K. K. Yang, “Equalizer Design and Performance Trade-Offs in ADC-Based Serial Links,” IEEE Trans. Circuits Syst. I, vol. 58, no. 9, pp. 2096–2107, Sep. 2011.

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