Lita Yang

From Murmann Mixed-Signal Group

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[[Image:LitaYang.jpg|160px|LitaYang.jpg]]  
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BSEE, Your University, 2012<br>  
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BSEE, California Institute of Technology, 2012<br>  
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'''Research''': ''Hardware Implementation and Optimization for Deep Belief Networks''
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MSEE, Stanford University, 2015
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Deep Belief Network (DBN) algorithms are used for pattern recognition tasks such as finding structure in large datasets including images, speech, and financial data. These algorithms yield state-of-the-art classification accuracy and learn to represent input data without using predefined features or supervised learning. Training these neuro-inspired networks, however, can be extremely time-consuming and limits the size and complexity of the models that can be used. To overcome this limitation, we suggest the implementation of DBNs in hardware, which can provide an efficient computational platform for applications in which speed, power, and area are stringent constraints. Though recent literature cites the use of GPUs and CPUs for massively parallelizing these algorithms to reduce computation time and cost, we believe an FPGA or ASIC implementation could be a more elegant solution to this problem. <br>
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Admitted to Ph.D. Candidacy: 2013-2014
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'''Email''': [mailto:yanglita@stanford.edu yanglita AT stanford DOT edu]<br>
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'''Research''': Approximate Memory for Energy-Efficient Machine Learning Algorithms&nbsp;
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<br> As transistor scaling is coming to a halt, systems today are becoming more and more power limited. Given recent trends in increasing network sizes and the need to process more data (such as Deep Learning and Big Data applications), the cost to store and move data around in a system can far exceed computation costs, prohibiting hardware implementations of machine learning algorithms in embedded applications.  
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Recently, there has been an emergence of interest in the field of Approximate Computing, which explores the performance (accuracy) of an algorithm with reduced precision. Convolutional Neural Networks (ConvNets), the current top performing image classification networks, are an example of a class of stochastic algorithms which can tolerate reduced precision for little degradation in algorithmic performance.&nbsp;We propose to reduce the system energy by exploiting error tolerance of the algorithm using approximate memory. From a memory designer’s perspective, this is rarely considered a viable option since most general purpose systems require robust storage and communication.
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We have shown that ConvNets are tolerant to bit flips and reduction in precision [1]. To accurately quantify the effectiveness of accepting bit errors under reduced memory supply voltages during ConvNet inference and training, we took measurements on an 8KB SRAM test chip in 28nm UTBB FD-SOI CMOS for emulating memory bit errors at low voltages [2]. The results demonstrate supply voltage reduction of 310mV on a MNIST ConvNet, resulting in 5.4x leakage power savings and 2.9x memory access power savings at 99% of floating-point classification accuracy, with no additional hardware cost.
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<br>&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;&nbsp;[[Image:HILMemory.png]]<br>
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[1] B. Murmann, D. Bankman, E. Chai, D. Miyashita, and L. Yang, "Mixed-Signal Circuits for Embedded Machine-Learning Applications," Asilomar Conference on Signals, Systems and Computers, Asilomar, CA, Nov. 2015.
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[2] L. Yang and B. Murmann, "SRAM Voltage Scaling for Energy-Efficient Convolutional Neural Networks," International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, Mar. 2017, pp. 7-12.

Revision as of 07:51, 19 July 2017

LitaYang.jpg

BSEE, California Institute of Technology, 2012

MSEE, Stanford University, 2015

Admitted to Ph.D. Candidacy: 2013-2014

Email: yanglita AT stanford DOT edu

Research: Approximate Memory for Energy-Efficient Machine Learning Algorithms 


As transistor scaling is coming to a halt, systems today are becoming more and more power limited. Given recent trends in increasing network sizes and the need to process more data (such as Deep Learning and Big Data applications), the cost to store and move data around in a system can far exceed computation costs, prohibiting hardware implementations of machine learning algorithms in embedded applications.

Recently, there has been an emergence of interest in the field of Approximate Computing, which explores the performance (accuracy) of an algorithm with reduced precision. Convolutional Neural Networks (ConvNets), the current top performing image classification networks, are an example of a class of stochastic algorithms which can tolerate reduced precision for little degradation in algorithmic performance. We propose to reduce the system energy by exploiting error tolerance of the algorithm using approximate memory. From a memory designer’s perspective, this is rarely considered a viable option since most general purpose systems require robust storage and communication.

We have shown that ConvNets are tolerant to bit flips and reduction in precision [1]. To accurately quantify the effectiveness of accepting bit errors under reduced memory supply voltages during ConvNet inference and training, we took measurements on an 8KB SRAM test chip in 28nm UTBB FD-SOI CMOS for emulating memory bit errors at low voltages [2]. The results demonstrate supply voltage reduction of 310mV on a MNIST ConvNet, resulting in 5.4x leakage power savings and 2.9x memory access power savings at 99% of floating-point classification accuracy, with no additional hardware cost.


                    HILMemory.png


[1] B. Murmann, D. Bankman, E. Chai, D. Miyashita, and L. Yang, "Mixed-Signal Circuits for Embedded Machine-Learning Applications," Asilomar Conference on Signals, Systems and Computers, Asilomar, CA, Nov. 2015.

[2] L. Yang and B. Murmann, "SRAM Voltage Scaling for Energy-Efficient Convolutional Neural Networks," International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, Mar. 2017, pp. 7-12.

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