Martin Johannes Krämer

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Martin Kraemer.JPG

Dipl.-Ing., TU Kaiserslautern, 2009
MSEE, Stanford University, 2011
Admitted to Ph.D. Candidacy: 2010 - 2011

Research: High-resolution SAR ADC using a source follower input buffer

Successive approximation register analog-to-digital converters (SAR ADCs) have moved to the center of research on low-power ADCs in the past several years, especially for low to moderate resolutions. This project focuses on extending the performance space of SAR ADCs to sampling rates of several tens of MHz at resolutions of fourteen bits or higher. At present, the main issues that prevent the realization of such an ADC are related to the input drive circuitry.


Since SAR ADCs must perform many bit decisions within one conversion cycle, only a short time window is left for input sampling. During this short sampling window, large transient currents are needed to charge and discharge the sampling capacitance, whose size is on the order of several picofarads to meet kT/C noise requirements. As a result, the input driver becomes a limiting factor, especially when it must be integrated on chip to circumvent ringing effects on parasitic bondwire inductances.


SF ADC2.jpg

                                                                                        Figure 1


While the aforementioned problem has been solved for pipeline ADCs using bipolar emitter followers [1], the required 100-300mW and also the extra cost for a BiCMOS process are unattractive. In this research, we aim for a solution that is compatible with fine-line CMOS using integrated source follower (SF) buffers (see Figure 1). In order to meet the target specs for the SF buffers, we investigate a linearity enhancement technique that places the buffer inside the successive approximation loop [2].Circuit and system simulations indicate that it is possible to use a simple source follower without any additional circuitry while still meeting 14 bit linearity. This allows us to save a significant portion of the buffer power, since we can design the SF for speed only and do not need to invest additional power for linearity improvement.


We are currently working on the layout of a prototype to prove the concept with real measurments.
                                                                                                                                                                     


[1] A.M.A Ali, A. Morgan, C. Dillon, G. Patterson, S. Puckett, M. Hensley, R. Stop, P. Bhoraskar, S. Bardsley, D. Lattimore, J. Bray, C. Speir, R. Sneed, "A 16b 250MS/s IF-sampling pipelined A/D converter with background calibration," ISSCC Dig. Tech. Papers, San Francisco, CA, Feb.    2010, pp.292-293.

[2] K. Doris, E. Janssen, C. Nani, A. Zanikopoulos, G. van der Weide, "A 480 mW 2.6 GS/s 10b Time-Interleaved ADC With 48.5 dB SNDR up to Nyquist in 65 nm CMOS," Solid-State Circuits, IEEE J. Solid-State Circuits, vol.46, no.12, pp. 2821-2833, Dec. 2011

 
Email: mkramerm AT stanford DOT edu

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