# Publications

### From Murmann Mixed-Signal Group

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== 2011 == | == 2011 == | ||

- | *R. Nguyen, C. Raynaud, A. Cathelin, and B. Murmann, "A 6.7-ENOB, 500-MS/s, 5.1-mW Dynamic Pipeline ADC in 65-nm SOI CMOS," to appear | + | *R. Nguyen, C. Raynaud, A. Cathelin, and B. Murmann, "A 6.7-ENOB, 500-MS/s, 5.1-mW Dynamic Pipeline ADC in 65-nm SOI CMOS," to appear in Proc. ESSCIRC, Helsinki, Finland, Sep. 2011. |

- | *R.M. Walker, H. Gao, P. Nuyujukian, K. Makinwa, K.V. Shenoy, T. Meng, and B. Murmann, "A 96-Channel Full Data Rate Direct Neural Interface in 0.13µm CMOS," in Symp. VLSI Circuits Dig., Kyoto, Japan, Jun. 2011. | + | *R.M. Walker, H. Gao, P. Nuyujukian, K. Makinwa, K.V. Shenoy, T. Meng, and B. Murmann, "A 96-Channel Full Data Rate Direct Neural Interface in 0.13µm CMOS," in Symp. VLSI Circuits Dig., Kyoto, Japan, Jun. 2011, pp. 144-145. |

- | *D.A. Hall, R.S. Gaster, S.J. Osterfeld, K. Makinwa, S.X. Wang, and B. Murmann, "A 256 Channel Magnetoresistive Biosensor Microarray for Quantitative Proteomics," in Symp. VLSI Circuits Dig., Kyoto, Japan, Jun. 2011. | + | *D.A. Hall, R.S. Gaster, S.J. Osterfeld, K. Makinwa, S.X. Wang, and B. Murmann, "A 256 Channel Magnetoresistive Biosensor Microarray for Quantitative Proteomics," in Symp. VLSI Circuits Dig., Kyoto, Japan, Jun. 2011, pp. 174-175. |

- | *D. Kim, T. Matsuura, and B. Murmann, "A Continuous-Time, Jitter Insensitive ∑∆ Modulator Using a Digitally Linearized Gm-C Integrator with Embedded SC Feedback DAC," in Symp. VLSI Circuits Dig., Kyoto, Japan, Jun. 2011. | + | *D. Kim, T. Matsuura, and B. Murmann, "A Continuous-Time, Jitter Insensitive ∑∆ Modulator Using a Digitally Linearized Gm-C Integrator with Embedded SC Feedback DAC," in Symp. VLSI Circuits Dig., Kyoto, Japan, Jun. 2011, pp. 38-39. |

*B. Murmann and M. El-Chammas, "Background Calibration of Timing Skew in Time-Interleaved A/D Converters," International Conference on Sampling Theory and Applications (SampTA), Singapore, May 2011. [http://sampta2011.ntu.edu.sg/cms/program/paperDetails.asp?PaperID=132] | *B. Murmann and M. El-Chammas, "Background Calibration of Timing Skew in Time-Interleaved A/D Converters," International Conference on Sampling Theory and Applications (SampTA), Singapore, May 2011. [http://sampta2011.ntu.edu.sg/cms/program/paperDetails.asp?PaperID=132] | ||

*M. El-Chammas and B. Murmann, “A 12-GS/s 81-mW 5-bit Time-Interleaved Flash ADC With Background Timing Skew Calibration,” IEEE J. Solid-State Circuits, vol. 46, no. 4, pp. 838-847, Apr. 2011. [http://dx.doi.org/10.1109/JSSC.2011.2108125] | *M. El-Chammas and B. Murmann, “A 12-GS/s 81-mW 5-bit Time-Interleaved Flash ADC With Background Timing Skew Calibration,” IEEE J. Solid-State Circuits, vol. 46, no. 4, pp. 838-847, Apr. 2011. [http://dx.doi.org/10.1109/JSSC.2011.2108125] | ||

- | *Y. Chung, E. Verploegen, A. Vailionis, Y. Sun, Y. Nishi, B. Murmann, and Z. Bao, “Controlling Electric Dipoles in Nanodielectrics and | + | *Y. Chung, E. Verploegen, A. Vailionis, Y. Sun, Y. Nishi, B. Murmann, and Z. Bao, “Controlling Electric Dipoles in Nanodielectrics and its Applications for Enabling Air-Stable n-Channel Organic Transistors,” Nano Letters, vol. 11, no. 3, pp. 1161-1165, Mar. 2011. [http://dx.doi.org/10.1021/nl104087u] |

*T. Konishi, K. Inazu, J.G. Lee, M. Natsui, S. Masui, and B. Murmann, “Design Optimization of High-Speed and Low-Power Operational Transconductance Amplifier Using g<sub>m</sub>/I<sub>D</sub> Lookup Table Methodology,” IEICE Trans. Electronics, vol. E94-C, no. 3, pp. 334-345, Mar. 2011. [http://dx.doi.org/10.1587/transele.E94.C.334] | *T. Konishi, K. Inazu, J.G. Lee, M. Natsui, S. Masui, and B. Murmann, “Design Optimization of High-Speed and Low-Power Operational Transconductance Amplifier Using g<sub>m</sub>/I<sub>D</sub> Lookup Table Methodology,” IEICE Trans. Electronics, vol. E94-C, no. 3, pp. 334-345, Mar. 2011. [http://dx.doi.org/10.1587/transele.E94.C.334] | ||

*S. Hori and B. Murmann, “Feedforward Interference Cancellation Architecture for Short-Range Wireless Communication,” IEEE Trans. Circuits Syst. II, vol. 58, no. 1, pp. 16-20, Jan. 2011. [http://dx.doi.org/10.1109/TCSII.2010.2092828] | *S. Hori and B. Murmann, “Feedforward Interference Cancellation Architecture for Short-Range Wireless Communication,” IEEE Trans. Circuits Syst. II, vol. 58, no. 1, pp. 16-20, Jan. 2011. [http://dx.doi.org/10.1109/TCSII.2010.2092828] |

## Revision as of 23:57, 2 September 2011

## Contents |

## 2011

- R. Nguyen, C. Raynaud, A. Cathelin, and B. Murmann, "A 6.7-ENOB, 500-MS/s, 5.1-mW Dynamic Pipeline ADC in 65-nm SOI CMOS," to appear in Proc. ESSCIRC, Helsinki, Finland, Sep. 2011.
- R.M. Walker, H. Gao, P. Nuyujukian, K. Makinwa, K.V. Shenoy, T. Meng, and B. Murmann, "A 96-Channel Full Data Rate Direct Neural Interface in 0.13µm CMOS," in Symp. VLSI Circuits Dig., Kyoto, Japan, Jun. 2011, pp. 144-145.
- D.A. Hall, R.S. Gaster, S.J. Osterfeld, K. Makinwa, S.X. Wang, and B. Murmann, "A 256 Channel Magnetoresistive Biosensor Microarray for Quantitative Proteomics," in Symp. VLSI Circuits Dig., Kyoto, Japan, Jun. 2011, pp. 174-175.
- D. Kim, T. Matsuura, and B. Murmann, "A Continuous-Time, Jitter Insensitive ∑∆ Modulator Using a Digitally Linearized Gm-C Integrator with Embedded SC Feedback DAC," in Symp. VLSI Circuits Dig., Kyoto, Japan, Jun. 2011, pp. 38-39.
- B. Murmann and M. El-Chammas, "Background Calibration of Timing Skew in Time-Interleaved A/D Converters," International Conference on Sampling Theory and Applications (SampTA), Singapore, May 2011. [1]
- M. El-Chammas and B. Murmann, “A 12-GS/s 81-mW 5-bit Time-Interleaved Flash ADC With Background Timing Skew Calibration,” IEEE J. Solid-State Circuits, vol. 46, no. 4, pp. 838-847, Apr. 2011. [2]
- Y. Chung, E. Verploegen, A. Vailionis, Y. Sun, Y. Nishi, B. Murmann, and Z. Bao, “Controlling Electric Dipoles in Nanodielectrics and its Applications for Enabling Air-Stable n-Channel Organic Transistors,” Nano Letters, vol. 11, no. 3, pp. 1161-1165, Mar. 2011. [3]
- T. Konishi, K. Inazu, J.G. Lee, M. Natsui, S. Masui, and B. Murmann, “Design Optimization of High-Speed and Low-Power Operational Transconductance Amplifier Using g
_{m}/I_{D}Lookup Table Methodology,” IEICE Trans. Electronics, vol. E94-C, no. 3, pp. 334-345, Mar. 2011. [4] - S. Hori and B. Murmann, “Feedforward Interference Cancellation Architecture for Short-Range Wireless Communication,” IEEE Trans. Circuits Syst. II, vol. 58, no. 1, pp. 16-20, Jan. 2011. [5]

## 2010

- C. Daigle, A. Dastgheib, and B. Murmann, “A 12-bit 800-MS/s switched-capacitor DAC with open-loop output driver and digital predistortion,” in Proc. IEEE Asian Solid State Circuits Conf., Nov. 2010, pp. 1-4. [6]
- B. Murmann and W. Xiong, “Design of analog circuits using organic field-effect transistors,” in Proc. ICCAD, San Jose, CA, Nov. 2010, pp. 504-507. [7]
- J. Jeon, B. Murmann, and Z. Bao, “Full-Swing and High-Gain Pentacene Logic Circuits on Plastic Substrate,” IEEE Electron Device Letters, vol. 31, no. 12, pp. 1488-1490, Nov. 2010. [8]
- J. Kim and B. Murmann, “A 12-bit, 30-MS/s, 2.95-mW pipelined ADC using single-stage class-AB amplifiers and deterministic background calibration,” in Proc. ESSCIRC, Sevilla, Spain, Sep. 2010, pp. 378-381. [9]
- W. Xiong, Y. Guo, U. Zschieschang, H. Klauk, and B. Murmann, “A 3-V, 6-Bit C-2C Digital-to-Analog Converter Using Complementary Organic Thin-Film Transistors on Glass,” IEEE J. Solid-State Circuits, vol. 45, no. 7, pp. 1380-1388, Jul. 2010. [10]
- M. El-Chammas and B. Murmann, “A 12-GS/s 81-mW 5-bit time-interleaved flash ADC with background timing skew calibration,” in Symp. VLSI Circuits Dig., Honolulu, HI, Jun. 2010, pp. 157-158. [11]
- R. Nguyen and B. Murmann, “The Design of Fast-Settling Three-Stage Amplifiers Using the Open-Loop Damping Factor as a Design Parameter,” IEEE Trans. Circuits Syst. I, vol. 57, no. 6, pp. 1244-1254, Jun. 2010. [12]
- B. Murmann, “Trends in Low-Power, Digitally Assisted A/D Conversion,” IEICE Trans. Electronics, vol. E93-C, no. 6, pp. 718-729, Jun. 2010. [13]
- D.A. Hall, R.S. Gaster, S.X. Wang, and B. Murmann, “Portable biomarker detection with magnetic nanotags,” in Proc. IEEE Int. Symp. Circuits Syst., Paris, France, May 2010, pp. 1779-1782. [14]
- D. Hall, R. Gaster, S. Osterfeld, B. Murmann, and S. Wang, “GMR biosensor arrays: Correction techniques for reproducibility and enhanced sensitivity,” Biosensors and Bioelectronics, vol. 25, no. 9, pp. 2177-2181, May 2010. [15]
- D. Hall, R. Gaster, T. Lin, S. Osterfeld, S. Han, B. Murmann, and S. Wang, “GMR biosensor arrays: A system perspective,” Biosensors and Bioelectronics, vol. 25, no. 9, pp. 2051-2057, May 2010. [16]
- Y. Chung, B. Murmann, S. Selvarasah, M.R. Dokmeci, and Z. Bao, “Low-voltage and short-channel pentacene field-effect transistors with top-contact geometry using parylene-C shadow masks,” Appl. Phys. Lett., vol. 96, no. 13, p. 133306 (3 pages), Mar. 2010. [17]
- W. Xiong, U. Zschieschang, H. Klauk, and B. Murmann, “A 3V 6b successive-approximation ADC using complementary organic thin-film transistors on glass,” in ISSCC Dig. Tech. Papers, San Francisco, CA, Feb. 2010, pp. 134-135. [18]

## 2009

- R.S. Gaster, D.A. Hall, C.H. Nielsen, S.J. Osterfeld, H. Yu, K.E. Mach, R.J. Wilson, B. Murmann, J.C. Liao, S.S. Gambhir, and S.X. Wang, “Matrix-insensitive protein assays push the limits of biosensors in medicine,” Nature Medicine, vol. 15, no. 11, pp. 1327-1332, Nov. 2009. [19]
- W. Xiong, Y. Guo, U. Zschieschang, H. Klauk, and B. Murmann, “A 3-V, 6-bit C-2C digital-to-analog converter using complementary organic thin-film transistors on glass,” in Proc. ESSCIRC, Athens, Greece, Sep. 2009, pp. 212-215. [20]
- J. Salvia, P. Lajevardi, M. Hekmat, and B. Murmann, “A 56MΩ CMOS TIA for MEMS applications,” in Proc. IEEE Custom Integrated Circuits Conf., San Jose, CA, Sep. 2009, pp. 199-202. [21]
- P. Nikaeen and B. Murmann, “Digital Compensation of Dynamic Acquisition Errors at the Front-End of High-Performance A/D Converters,” IEEE J. Selected Topics in Signal Processing, vol. 3, no. 3, pp. 499-508, Jun. 2009. [22]
- M. El-Chammas and B. Murmann, “General Analysis on the Impact of Phase-Skew in Time-Interleaved ADCs,” IEEE Trans. Circuits Syst. I, vol. 56, no. 5, pp. 902-910, May 2009. [23]
- J. Hu, N. Dolev, and B. Murmann, “A 9.4-bit, 50-MS/s, 1.44-mW Pipelined ADC Using Dynamic Source Follower Residue Amplification,” IEEE J. Solid-State Circuits, vol. 44, no. 4, pp. 1057-1066, Apr. 2009. [24]
- T. Sundstrom, B. Murmann, and C. Svensson, “Power Dissipation Bounds for High-Speed Nyquist Analog-to-Digital Converters,” IEEE Trans. Circuits Syst. I, vol. 56, no. 3, pp. 509-518, Mar. 2009. [25]
- J. Salvia, R. Melamud, S. Chandorkar, H. Lee, Y. Qu, S. Lord, B. Murmann, and T. Kenny, “Phase Lock Loop based Temperature Compensation for MEMS Oscillators,” in Proc. IEEE MEMS, Sorrento, Italy, Jan. 2009, pp. 661-664. [26]

## 2008

- J. Salvia, M. Messana, M. Ohline, M. Hopcroft, R. Melamud, S. Chandorkar, H. Lee, G. Bahl, B. Murmann, and T. Kenny, “Exploring the limits and practicality of Q-based temperature compensation for silicon resonators,” in IEDM Tech. Dig., San Francisco, CA, Dec. 2008, pp. 1-4. [27]
- A. Dastgheib and B. Murmann, “Calculation of Total Integrated Noise in Analog Circuits,” IEEE Trans. Circuits Syst. I, vol. 55, no. 10, pp. 2988-2993, Nov. 2008. [28]
- P. Nikaeen and B. Murmann, “Digital correction of dynamic track-and-hold errors providing SFDR > 83 dB up to fin = 470 MHz,” in Proc. IEEE Custom Integrated Circuits Conf., San Jose, CA, Sep. 2008, pp. 161-164. [29]
- B. Murmann, “A/D converter trends: Power dissipation, scaling and digitally assisted architectures,” in Proc. IEEE Custom Integrated Circuits Conf., San Jose, CA, Sep. 2008, pp. 105-112. [30]
- J. Hu, N. Dolev, and B. Murmann, “A 9.4-bit, 50-MS/s, 1.44-mW pipelined ADC using dynamic residue amplification,” in Symp. VLSI Circuits Dig., Honolulu, HI, Jun. 2008, pp. 216-217. [31]
- B. Murmann, C. Vogel, and H. Koeppl, “Digitally enhanced analog circuits: System aspects,” in Proc. IEEE Int. Symp. Circuits Syst., Seattle, WA, May 2008, pp. 560-563. [32]
- M. El-Chammas and B. Murmann, “General analysis on the impact of phase-skew in time-interleaved ADCs,” in Proc. IEEE Int. Symp. Circuits Syst., Seattle, WA, May 2008, pp. 17-20. [33]
- A. Abusleme and B. Murmann, “Predictive control algorithm for phase-locked loops,” in Proc. IEEE Int. Symp. Circuits Syst., Seattle, WA, May 2008, pp. 1528-1531. [34]
- M. Agarwal, S.A. Chandorkar, H. Mehta, R.N. Candler, B. Kim, M.A. Hopcroft, R. Melamud, C.M. Jha, G. Bahl, G. Yama, T.W. Kenny, and B. Murmann, “A study of electrostatic force nonlinearities in resonant microstructures,” Appl. Phys. Lett., vol. 92, no. 10, p. 104106 (3 pages), Mar. 2008. [35]
- P. Nikaeen, B. Murmann, and R. Dutton, “Characterizing the Impact of Substrate Noise on High-Speed Flash ADCs,” in Proc. ISQED, San Jose, CA, Mar. 2008, pp. 396-400. [36]
- J.W. Kim, B. Murmann, and R. Dutton, “Hybrid Integration of Bandgap Reference Circuits Using Silicon ICs and Germanium Devices,” in Proc. ISQED, San Jose, CA, Mar. 2008, pp. 429-432. [37]

## 2007

- B. Murmann and B. Boser, “Digital Domain Measurement and Cancellation of Residue Amplifier Nonlinearity in Pipelined ADCs,” IEEE Trans. Instrum. Meas., vol. 56, no. 6, pp. 2504-2514, Dec. 2007. [38]
- M. Agarwal, H. Mehta, R.N. Candler, S.A. Chandorkar, B. Kim, M.A. Hopcroft, R. Melamud, G. Bahl, G. Yama, T.W. Kenny, and B. Murmann, “Scaling of amplitude-frequency-dependence nonlinearities in electrostatically transduced microresonators,” J. Appl. Phys., vol. 102, no. 7, p. 074903 (7 pages), Oct. 2007. [39]
- Y. Oh and B. Murmann, “A Low-Power, 6-bit Time-Interleaved SAR ADC Using OFDM Pilot Tone Calibration,” in Proc. IEEE Custom Integrated Circuits Conf., San Jose, CA, Sep. 2007, pp. 193-196. [40]
- E. Iroaga and B. Murmann, “A 12-Bit 75-MS/s Pipelined ADC Using Incomplete Settling,” IEEE J. Solid-State Circuits, vol. 42, no. 4, pp. 748-756, Apr. 2007. [41]
- Shu-Jen Han, Heng Yu, B. Murmann, N. Pourmand, and S. Wang, “A High-Density Magnetoresistive Biosensor Array with Drift-Compensation Mechanism,” in ISSCC Dig. Tech. Papers, San Francisco, CA, Feb. 2007, pp. 168-594. [42]
- M. Agarwal, K.K. Park, S.A. Chandorkar, R.N. Candler, B. Kim, M.A. Hopcroft, R. Melamud, T.W. Kenny, and B. Murmann, “Acceleration sensitivity in beam-type electrostatic microresonators,” Appl. Phys. Lett., vol. 90, no. 1, p. 014103 (3 pages), Jan. 2007. [43]
- M. Agarwal, H. Mehta, R. Candler, S. Chandorkar, Bongsang Kim, M. Hopcroft, R. Melamud, G. Bahl, G. Yama, T. Kenny, and B. Murmann, “Impact of miniaturization on the current handling of electrostatic MEMS resonators,” in Proc. IEEE MEMS, Kobe, Japan, Jan. 2007, pp. 783-786. [44]

## 2006

- A. Nikoozadeh and B. Murmann, “An Analysis of Latch Comparator Offset Due to Load Capacitor Mismatch,” IEEE Trans. Circuits Syst. II, vol. 53, no. 12, pp. 1398-1402, Dec. 2006. [45]
- M. Agarwal, S.A. Chandorkar, R.N. Candler, B. Kim, M.A. Hopcroft, R. Melamud, C.M. Jha, T.W. Kenny, and B. Murmann, “Optimal drive condition for nonlinearity reduction in electrostatic microresonators,” Appl. Phys. Lett., vol. 89, no. 21, p. 214105 (3 pages), Nov. 2006. [46]
- B. Murmann, “Digitally Assisted Analog Circuits,” in Proc. IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software, Dallas, Tx, Oct. 2006, pp. 23-30. [47]
- J. Chun and B. Murmann, “Analysis and Measurement of Signal Distortion due to ESD Protection Circuits,” IEEE J. Solid-State Circuits, vol. 41, no. 10, pp. 2354-2358, Oct. 2006. [48]
- B. Murmann, P. Nikaeen, D. Connelly, and R. Dutton, “Impact of Scaling on Analog Performance and Associated Modeling Needs,” IEEE Trans. Electron Dev., vol. 53, no. 9, pp. 2160-2167, Sep. 2006. [49]
- Y. Oh and B. Murmann, “System embedded ADC calibration for OFDM receivers,” IEEE Trans. Circuits Syst. I, vol. 53, no. 8, pp. 1693-1703, Aug. 2006. [50]
- B. Sheahan, J. Fattaruso, J. Wong, K. Muth, and B. Murmann, “4.25 Gb/s laser driver: design challenges and EDA tool limitations,” in Proc. Design Automation Conference, San Francisco, CA, Jul. 2006, pp. 863-866. [51]
- E. Iroaga and B. Murmann, “A 12b, 75MS/s Pipelined ADC Using Incomplete Settling,” in Symp. VLSI Circuits Dig., Honolulu, HI, Jun. 2006, pp. 222-223. [52]
- M. Agarwal, K.K. Park, R.N. Candler, B. Kim, M.A. Hopcroft, S.A. Chandorkar, C.M. Jha, R. Melamud, T.W. Kenny, and B. Murmann, “Nonlinear Characterization of Electrostatic MEMS Resonators,” in Proc. IEEE Int. Freq. Control Symp., Miami, FL, Jun. 2006, pp. 209-212. [53]
- B. Murmann, “Digitally Assisted Analog Circuits,” IEEE Micro, vol. 26, no. 2, pp. 38-47, Mar. 2006. [54]
- M.A. Hopcroft, M. Agarwal, K.K. Park, B. Kim, C.M. Jha, R.N. Candler, G. Yama, B. Murmann, and T.W. Kenny, “Temperature Compensation of a MEMS Resonator Using Quality Factor as a Thermometer,” in Proc. IEEE MEMS, Istanbul, Turkey, Jan. 2006, pp. 222-225. [55]
- M. Agarwal, K.K. Park, M. Hopcroft, S. Chandorkar, R.N. Candler, B. Kim, R. Melamud, G. Yama, B. Murmann, and T.W. Kenny, “Effects of Mechanical Vibrations and Bias Voltage Noise on Phase Noise of MEMS Resonator Based Oscillators,” in Proc. IEEE MEMS, Istanbul, Turkey, Jan. 2006, pp. 154-157. [56]

## 2005

- M. Agarwal, K. Park, R. Candler, M. Hopcroft, C. Jha, R. Melamud, B. Kim, B. Murmann, and T. Kenny, “Non-linearity cancellation in MEMS resonators for improved power-handling,” in IEDM Tech. Dig., San Francisco, CA, Dec. 2005, pp. 286-289. [57]
- E. Iroaga, L. Nathawad, and B. Murmann, “A background correction technique for timing errors in time-interleaved analog-to-digital converters,” in Proc. IEEE Int. Symp. Circuits Syst., Kobe, Japan, May 2005, vol. 6, pp. 5557-5560. [58]
- S. Arekapudi, E. Iroaga, and B. Murmann, “A low-power distributed wide-band LNA in 0.18 μm CMOS,” in Proc. IEEE Int. Symp. Circuits Syst., Kobe, Japan, May 2005, vol. 5, pp. 5055-5058. [59]

## 2004

- B. Murmann, “A/D Conversion gets a Digital Assist,” EE Times, September 27, 2004. [60]
- B. Murmann and B. Boser, “Digitally Assisted Analog Integrated Circuits,” ACM Queue, vol. 2, no. 1, pp. 64-71, Mar. 2004. [61]

## 2003

- B. Murmann and B. Boser, “A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification,” IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2040-2050, Dec. 2003. [62]
- B. Murmann and B. Boser, “A 12 b 75 MS/s pipelined ADC using open-loop residue amplification,” in ISSCC Dig. Tech. Papers, San Francisco, CA, Feb. 2003, pp. 328-329. [63]

## Books and Book Chapters

- B. Murmann, “Low-Power Pipelined A/D Conversion,” in Analog Circuit Design, by M. Steyaert, A.H.M. Roermund, A. Baschirotto (eds.), Springer, 2011. [64]
- M. Keller, B. Murmann, and Y. Manoli, "Analog-Digital Interfaces," in CHIPS 2020, by B. Hoefflinger (ed.), Springer, 2012. [65]
- B. Murmann, “Limits on ADC Power Dissipation,” in Analog Circuit Design, by M. Steyaert, A.H.M. Roermund, J.H. van Huijsing (eds.), Springer, 2006. [66]
- B. Murmann and B. E. Boser, Digitally Assisted Pipeline ADCs: Kluwer Academic Publishers, 2004. [67]

## PhD Theses

- P. Nikaeen, "Digital compensation of dynamic acquisition errors at the front-end of ADCs," 2008. [68]
- J. Hu, "Low-power dynamic amplifiers for pipelined A/D conversion," 2008. [69]
- Y. Oh, "A/D converters with system embedded calibration for wireless applications," 2007. [70]
- E. Iroaga, "Pipelined analog-to-digital converters using incomplete settling," 2006. [71]