Ryan Boesch

From Murmann Mixed-Signal Group

(Difference between revisions)
Jump to: navigation, search
 
(14 intermediate revisions not shown)
Line 1: Line 1:
-
[[Image:RyanBoesch.jpg|160px]]  
+
[[Image:RyanBoesch.jpg]]<br>  
-
 
+
-
<br>  
+
BSEE, Iowa State University, 2008<br>MSEE, Iowa State University, 2009<br>Admitted to Ph.D. Candidacy: 2009-2010  
BSEE, Iowa State University, 2008<br>MSEE, Iowa State University, 2009<br>Admitted to Ph.D. Candidacy: 2009-2010  
-
'''Research''': ''Wide-Band Continuous-Time Low-Pass Filter with Linearity Feedback Correction for OFDM Systems''<br>
+
'''Research''': ''High Speed Analog Filters and Equalizers''<br>  
-
The next-generation wireless communications systems are targeting the 60GHz band to meet the data rate requirements for a wire-free world. Driven by stringent requirements on blocker rejection, these systems call for highly linear integrated active filters with bandwidths on the order of 1GHz which have yet to be reported in literature.Most proposed 60GHz band specifications rely on orthogonal frequency-division multiplexing (OFDM). OFDM systems use pilot tones for channel estimation and calibration purposes. These pilot tones also contain information about the signal path nonlinearity that can be used in a feedback path to correct the filter nonlinearities. It is anticipated that, with this feedback correction, filters with the stringent required specifications for 60GHz band applications will be realizable in modern CMOS processes.
 
-
We are currently researching the bounds on linearity correction for ultra-wideband Gm-C filters as well as developing a robost nonlinearity correction algorithm for filters in OFDM systems.&nbsp;<br>
 
-
[[Image:Ryan diagram.png|670px]]<br>  
+
As high-speed links push for higher and higher throughputs, the increasing baud rate and signal bandwidth make it challenging and costly to equalize entirely in digital domain. Because of this fact there are now opportunities to perform some of the equalization in the energy efficient analog domain. Recent publications (Momtaz et al., JSSC 2010) have implemented feed-forward equalizers (FFEs) but have relied heavily on area expensive inductors and high power circuits. In this project, we are building a FFE equalizer using only inverters and capacitors. It is highly efficient due to the class AB operation of the inverter transconductors. Also, there are a low number of parasitic nodes, which translates to high bandwidth with no need for inductive peaking.
 +
 
 +
 
 +
 
 +
To account for the process, voltage, and temperature variations, a novel switched capacitor master/slave biasing circuit has been designed to perform background calibration of the delay cells. Postlayout simulations have shown state of the art performance in terms of power and noise, as well as area. The design is being fabricated in a TSMC40 process and will be tested during the summer 2015.
 +
 
 +
<br>  
-
'''Email''': [mailto:rboesch@stanford.edu rboesch AT stanford DOT edu]<br>
+
[[Image:Rboesch-researchsummary-July2014.png|center|300px|Rboesch-researchsummary-July2014.png]]'''Email''': [mailto:rboesch@stanford.edu rboesch@stanford.edu]<br>

Latest revision as of 10:24, 5 July 2015

RyanBoesch.jpg

BSEE, Iowa State University, 2008
MSEE, Iowa State University, 2009
Admitted to Ph.D. Candidacy: 2009-2010

Research: High Speed Analog Filters and Equalizers


As high-speed links push for higher and higher throughputs, the increasing baud rate and signal bandwidth make it challenging and costly to equalize entirely in digital domain. Because of this fact there are now opportunities to perform some of the equalization in the energy efficient analog domain. Recent publications (Momtaz et al., JSSC 2010) have implemented feed-forward equalizers (FFEs) but have relied heavily on area expensive inductors and high power circuits. In this project, we are building a FFE equalizer using only inverters and capacitors. It is highly efficient due to the class AB operation of the inverter transconductors. Also, there are a low number of parasitic nodes, which translates to high bandwidth with no need for inductive peaking.


To account for the process, voltage, and temperature variations, a novel switched capacitor master/slave biasing circuit has been designed to perform background calibration of the delay cells. Postlayout simulations have shown state of the art performance in terms of power and noise, as well as area. The design is being fabricated in a TSMC40 process and will be tested during the summer 2015.


Rboesch-researchsummary-July2014.png
Email: rboesch@stanford.edu
Personal tools