Ryan Boesch

From Murmann Mixed-Signal Group

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[[Image:RyanBoesch.jpg|160px|RyanBoesch.jpg]]  
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[[Image:RyanBoesch.jpg]]<br>  
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BSEE, Iowa State University, 2008<br>MSEE, Iowa State University, 2009<br>Admitted to Ph.D. Candidacy: 2009-2010  
BSEE, Iowa State University, 2008<br>MSEE, Iowa State University, 2009<br>Admitted to Ph.D. Candidacy: 2009-2010  
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'''Research''': ''Nonlinearity in Ultra-Wideband Low-Pass Filters''<br>  
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'''Research''': ''High Speed Analog Filters and Equalizers''<br>  
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Due to decreasing supply voltage and increasing device output conductance in modern short channel CMOS processes, designing a linear analog filter is becoming increasingly challenging. Furthermore, modern communications protocols like WiGig add additional challenges from their broadband input signals&nbsp;by requiring linearity over ultra-wide bandwidths (UWB). My research studies nonlinearities in UWB filters and tries to the address the problem by fully mathematically characterizing the nonlinearity, understanding its effect due to wideband inputs and not just a few test tones, and looking for ways to calibrate and correct for the nonlinearity in the analog domain.
 
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We are currently working towards the tapeout of an analog feed forward equalizer (FFE) using Gm-C filters in 45nm CMOS. This chip will be a vehicle to demonstrate the wideband nonlinearity theory that has already been worked out in this research.
 
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[[Image:ResearchOverviewRyanJuly2013.png|400px|ResearchOverviewRyanJuly2013.png]]<br>  
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As high-speed links push for higher and higher throughputs, the increasing baud rate and signal bandwidth make it challenging and costly to equalize entirely in digital domain. Because of this fact there are now opportunities to perform some of the equalization in the energy efficient analog domain. Recent publications (Momtaz et al., JSSC 2010) have implemented feed-forward equalizers (FFEs) but have relied heavily on area expensive inductors and high power circuits. In this project, we are building a FFE equalizer using only inverters and capacitors. It is highly efficient due to the class AB operation of the inverter transconductors. Also, there are a low number of parasitic nodes, which translates to high bandwidth with no need for inductive peaking.
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To account for the process, voltage, and temperature variations, a novel switched capacitor master/slave biasing circuit has been designed to perform background calibration of the delay cells. Postlayout simulations have shown state of the art performance in terms of power and noise, as well as area. The design is being fabricated in a TSMC40 process and will be tested during the summer 2015.
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'''Email''': [mailto:rboesch@stanford.edu rboesch AT stanford DOT edu]<br>
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[[Image:Rboesch-researchsummary-July2014.png|center|300px|Rboesch-researchsummary-July2014.png]]'''Email''': [mailto:rboesch@stanford.edu rboesch@stanford.edu]<br>

Latest revision as of 10:24, 5 July 2015

RyanBoesch.jpg

BSEE, Iowa State University, 2008
MSEE, Iowa State University, 2009
Admitted to Ph.D. Candidacy: 2009-2010

Research: High Speed Analog Filters and Equalizers


As high-speed links push for higher and higher throughputs, the increasing baud rate and signal bandwidth make it challenging and costly to equalize entirely in digital domain. Because of this fact there are now opportunities to perform some of the equalization in the energy efficient analog domain. Recent publications (Momtaz et al., JSSC 2010) have implemented feed-forward equalizers (FFEs) but have relied heavily on area expensive inductors and high power circuits. In this project, we are building a FFE equalizer using only inverters and capacitors. It is highly efficient due to the class AB operation of the inverter transconductors. Also, there are a low number of parasitic nodes, which translates to high bandwidth with no need for inductive peaking.


To account for the process, voltage, and temperature variations, a novel switched capacitor master/slave biasing circuit has been designed to perform background calibration of the delay cells. Postlayout simulations have shown state of the art performance in terms of power and noise, as well as area. The design is being fabricated in a TSMC40 process and will be tested during the summer 2015.


Rboesch-researchsummary-July2014.png
Email: rboesch@stanford.edu
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