Ryan Boesch

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[[Image:RyanBoesch.jpg]]<br>
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<br>Admitted to Ph.D. Candidacy: 2009-2010  
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BSEE, Iowa State University, 2008<br>MSEE, Iowa State University, 2009<br>Admitted to Ph.D. Candidacy: 2009-2010  
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'''Research''': ''Wide-Band Continuous-Time Low-Pass Filter with Linearity Feedback Correction for OFDM Systems''<br>The next-generation wireless communications systems are targeting the 60GHz band to meet the data rate requirements for a wire-free world. Driven by stringent requirements on blocker rejection and coexistence with other standards and protocols, systems will call for integrated active filters with bandwidths &gt; 1 GHz, pole quality factors exceeding 10, and filter linearity on the order of 60 dB. The objective of this project is to use digital information available in OFDM systems to perform background linearity calibration. OFDM systems presently use pilot tones for channel estimation and calibration purposes. These pilot tones contain spectral information about the signal path nonlinearity that will be used in a feedback path to correct the filter nonlinearities. It is anticipated that, with this feedback correction, filters with the stringent required specifications for 60GHz band applications will be realizable in modern CMOS processes.<br>  
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'''Research''': ''High Speed Analog Filters and Equalizers''<br>  
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OFDM is presently used in most modern communications standards and it will continue to be the modulation technique of choice for the foreseeable future. In addition to the target application for the 60GHz band, the linearity correction algorithm developed in this project will be applicable to all other present and future OFDM systems.<br>
 
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[[Image:Ryan_diagram.png|670px]]<br>
 
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'''Email''': [mailto:rboesch@stanford.edu rboesch AT stanford DOT edu]<br>
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As high-speed links push for higher and higher throughputs, the increasing baud rate and signal bandwidth make it challenging and costly to equalize entirely in digital domain. Because of this fact there are now opportunities to perform some of the equalization in the energy efficient analog domain. Recent publications (Momtaz et al., JSSC 2010) have implemented feed-forward equalizers (FFEs) but have relied heavily on area expensive inductors and high power circuits. In this project, we are building a FFE equalizer using only inverters and capacitors. It is highly efficient due to the class AB operation of the inverter transconductors. Also, there are a low number of parasitic nodes, which translates to high bandwidth with no need for inductive peaking.
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To account for the process, voltage, and temperature variations, a novel switched capacitor master/slave biasing circuit has been designed to perform background calibration of the delay cells. Postlayout simulations have shown state of the art performance in terms of power and noise, as well as area. The design is being fabricated in a TSMC40 process and will be tested during the summer 2015.
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[[Image:Rboesch-researchsummary-July2014.png|center|300px|Rboesch-researchsummary-July2014.png]]'''Email''': [mailto:rboesch@stanford.edu rboesch@stanford.edu]<br>

Latest revision as of 10:24, 5 July 2015

RyanBoesch.jpg

BSEE, Iowa State University, 2008
MSEE, Iowa State University, 2009
Admitted to Ph.D. Candidacy: 2009-2010

Research: High Speed Analog Filters and Equalizers


As high-speed links push for higher and higher throughputs, the increasing baud rate and signal bandwidth make it challenging and costly to equalize entirely in digital domain. Because of this fact there are now opportunities to perform some of the equalization in the energy efficient analog domain. Recent publications (Momtaz et al., JSSC 2010) have implemented feed-forward equalizers (FFEs) but have relied heavily on area expensive inductors and high power circuits. In this project, we are building a FFE equalizer using only inverters and capacitors. It is highly efficient due to the class AB operation of the inverter transconductors. Also, there are a low number of parasitic nodes, which translates to high bandwidth with no need for inductive peaking.


To account for the process, voltage, and temperature variations, a novel switched capacitor master/slave biasing circuit has been designed to perform background calibration of the delay cells. Postlayout simulations have shown state of the art performance in terms of power and noise, as well as area. The design is being fabricated in a TSMC40 process and will be tested during the summer 2015.


Rboesch-researchsummary-July2014.png
Email: rboesch@stanford.edu
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