Vaibhav Tripathi

From Murmann Mixed-Signal Group

Revision as of 11:36, 11 August 2012 by Vaibhavt (Talk | contribs)
Jump to: navigation, search


B.Tech, Electrical Engineering, Indian Institute of Technology, Kanpur, 2006
M.S, Electrical Engineering, Stanford University, 2009
Admitted to Ph.D. Candidacy: 2008-2009
Email: vaibhavt AT stanford DOT edu

Research: High speed and high resolution SAR ADC’s

Aggressive CMOS technology scaling over the last decade has resulted in faster switches and lower intrinsic gain. The latter has made it increasingly difficult to build high gain OTA’s. These high gain OTAs are critical components of Pipeline ADC’s which dominate the realm of medium-high resolution (12-14 bits) and high speed (100-250MHz). Hence, the potential benefits of technology scaling have not been completely tapped in such architectures. On the contrary, a SAR ADC uses a comparator, switches, digital logic and capacitors as circuit elements and the performance of each of these have improved with process scaling. This research focuses on exploring the SAR ADC architecture to improve both its conversion speed and resolution. We follow a two step approach: 1) Measuring matching characterics of small MOM caps [Chip 1] and (2) Evaluate the principle of Time Constant Matching to speed up DAC settling [Chip 2]. Learnings from these two chips will be used to envisage the goal of a 12 bit, 200-MS/s SAR ADC.

Chip 1 was taped out in July 2011 using the IBM 32nm SOI CMOS process and the silicon was received in April 2012. The chip has 96 test structures to measure the mismatch caharacteristics of small MOM caps. 48 test structures have a unit capacitance of 0.5fF while the other 48 have a unit capacitance of 1.5fF. Silicon measurements of this chip will commence soon.

In a SAR ADC, the conversion speed is essentially limited by the following three factors: (1) DAC array settling time, (2) Comparator decision time and (3) SAR logic delay. Time Constant Matching reduces (1) by appropriate matching of the pull up and pull down paths in the capacitive DAC. Chip 2 focuses on evaluating TCM and push the conversion speed of medium resolution SAR ADC's. An 8 bit, 400-MS/s prototype SAR ADC that uses TCM was designed in TSMC 65nm CMOS process and was taped out in March 2012. The ADC uses a unit capacitance of 0.75fF. Chip testing is currently in progress and preliminary measurements show promising performance.

                      Chip layout.JPG                              Time constant matching.jpg             Mom cap.jpg    A 0.75fF MOM capacitor

               Chip 1: Measuring mismatch characteristics of small MOM caps               Time Constant Matching Principle

Personal tools