Vaibhav Tripathi

From Murmann Mixed-Signal Group

Revision as of 07:44, 29 July 2013 by Vaibhavt (Talk | contribs)
Jump to: navigation, search

Vaibhav.jpg

B.Tech, Electrical Engineering, Indian Institute of Technology, Kanpur, 2006
M.S, Electrical Engineering, Stanford University, 2009
Admitted to Ph.D. Candidacy: 2008-2009
Email: vaibhavt AT stanford DOT edu

Research: High speed and high resolution SAR ADC’s

The successive approximation register (SAR) ADC architecture is attractive for integration in aggressively scaled CMOS, primarily since it does not rely on linear amplification blocks. This research focuses on exploring the SAR ADC architecture and aims to push the performance of SAR ADCs, targeting both high resolution (~12bits) and high speed (>150MHz) in 65nm CMOS technology.

We started with investigating the matching limit of small metal fringe capacitors that are used as unit elements in the capacitive DAC of a SAR ADC. Aggressive scaling of these unit capacitances allows the designer to set the input capacitance according to the thermal noise limit, resulting in lower switching energy and faster conversion speed. We fabricated a test structure in IBM 32nm SOI CMOS to measure the mismatch caharacteristics of small (~ 1 fF) metal fringe capacitors. Silicon measurement  of the chip have been completed and the results will appear in CICC 2013.

Next, in order to identify performance bottlenecks and thereby improve the conversion speed, we designed an 8 bit SAR ADC employing top plate sampling, loop delay optimization and asynchronous timing. The ADC was fabricated in TSMC 65nm CMOS process and used 0.75 fF custom designed metal fringe capacitors as unit elements in the DAC. The measured results show very good performance and will be published in ESSCIRC 2013.

In the final design, we investigate pipelining 2 SAR ADC’s with an efficient, open-loop inter-stage amplifier. Measurement results from the previous two test chips will help to decide the unit cap size for the ADC as well as provide a methodology to design fast and efficient medium resolution SAR A/D converters, which may be used as sub-ADC's in the pipelined architecture.

Top level block diagram vaibhav.JPG

Mom cap.jpg



                                                                 Fig. 1 A metal fringe capacitance (top)



Fig. 2. Pipelined SAR architecture (left)

Personal tools