Using Field Enhanced Oxidation of Amorphous Silicon for Gate Patterning
The method of amorphous silicon (a:Si) oxidation was used to pattern the critical gate level of a metal oxide semiconductor field-effect transistor (MOSFET). All other levels were patterned with conventional photolithography.
MOSFET Fabrication. The transistor was fabricated with a simplified four-mask process which started with a (100) p-type silicon wafer with a resistivity of 10-20 ohm-cm. The first step was the growth of a half micron layer of thermal oxide, called the "field oxide." We next opened a window in this layer by removing the field oxide over a rectangular area measuring 70 x 30 Ám. This area is called the "active region." The gate oxide was grown to a thickness of 87 ┼ and then 1000 ┼ of a:Si was deposited by low-pressure chemical vapor deposition (LPCVD). The a:Si deposits conformally on the existing oxide topography. It is this a:Si that we need to pattern with the AFM to create the transistor gate.
SEM micrograph of the continuous etched a:Si line traversing the oxide step edge.
Gate Lithography and Pattern Transfer. We hydrogen passivated the a:Si film by submersing the wafer in a 5:1 BOE solution for 4 min. The sample was then loaded into a standard Park Scientific Instruments AFM equipped with a silicon nitride cantilever coated with 300 ┼ of titanium. The AFM was used initially to image the transistor structure and determine the proper location to write the gate. We applied a 12 V bias to the a:Si while grounding the tip and moved the probe across the active area at a speed of 0.55 Ám/s. This created an oxide line 33 ┼ high and 0.21 Ám wide. The AFM-induced oxide pattern was then transferred into the a:Si by 1:1 SF6:Freon 115 plasma. The etching of the a:Si was monitored by laser interferometry, and the etch was terminated when the a:Si was completely etched.
Continuous Patterning Over Topography. We found that if the step edge between the active and field area is abrupt, the tip can pull off the surface. This results in a break of the line, which would make the transistor fail. Since the oxide line can be imaged immediately after patterning, this could be used to detect defects or breaks. Another solution is to create a more gradual step that the tip can easily follow. We used an isotropic etch to grade the oxide step between the field oxide and the gate oxide.
Results. The above figure is a SEM micrograph of the continuous etched a:Si line traversing the oxide step edge. Using this method for gate lithography, we successfully fabricated an nMOSFET with an effective channel length of 0.11 Ám. The electrical characteristics were reasonable with a transconductance of 279 mS/mm and a threshold voltage of 0.55 V.