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 100-nm pMOSFET Fabrication
Using Hybrid AFM / STM Lithography of Resist for Gate Patterning

We fabricated p-channel metal oxide semiconductor field effect transistors (pMOSFETs) using the method of hybrid AFM / STM lithography for gate level patterning. The gate level lithography required precise alignment capabilities, 100-nm resolution, and uniform patterning over transistor topography. Devices with 130-nm physical gate lengths and 100-nm effective channel lengths exhibited reasonable electrical characteristics. This pMOSFET fabrication demonstrates the capabilities of hybrid AFM / STM lithography and shows the systemís compatibility with semiconductor processing.

pMOSFET Fabrication Process

Gate Lithography

Continuous Exposure Over Active Area Topography

Uniform 100-nm Gate Over Topography

Device Characteristics

device fabrication

........pMOSFET fabrication process


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