100-nm pMOSFET Fabrication Gate Lithography

The gate patterning sequence is shown in the figure below. A negative-tone electron beam resist (SAL601) was spun over the polysilicon topography. The gray box represents the oxide contact pad that was previously patterned by photolithography.

Alignment. The resist was imaged with the AFM in contact mode to precisely locate the position where the gate would be written. This image was then imported into lithography software that controls the path and the speed of the tip. The closed loop feedback used in our scanner (Park Scientific Instruments Autoprobe M5) eliminates hysteresis and enables alignment accuracy of a few nanometers.

Exposure. Electrons emitted from a Ti-coated tip were used to expose the resist. Exposure was performed in the hybrid AFM / STM lithography mode in which both the tip-sample force and the emission current are held fixed. These dual feedback loops were essential for achieving uniform patterning over the topography.

Development and Pattern Transfer. The resist was developed in MF-322 for 10 min. Then the polysilicon was etched in a SF6 / Freon_115 plasma.

pMOSFET fabrication process.

.......patterning over active area topography

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