Bandwidth Extension in CMOS with Optimized On-Chip Inductors
S. S. Mohan, M. Hershenson, S. Boyd, and T. Lee
IEEE Journal of Solid-State Circuits, Special Issue on 1999 Custom Integrated Circuits Conferences, 35(3):346-355, March 2000.
We present a technique for enhancing the bandwidth of gigahertz broadband circuitry by using optimized on-chip spiral inductors as shunt-peaking elements. The series resistance of the on-chip inductor is incorporated as part of the load resistance to permit a large inductance to be realized with minimum area and capacitance. Simple, accurate inductance expressions are used in a lumped circuit inductor model to allow the passive and active components in the circuit to be simultaneously optimized. A quick and efficient global optimization method, based on geometric programming is discussed. The bandwidth extension technique is applied in the implementation of a 2.125Gbaud preamplifier that employs a common-gate input stage followed by a cascoded common-source stage. On-chip shunt-peaking is introduced at the dominant pole to improve the overall system performance, including a 40% increase in the transimpedance. This implementation achieves a 1.6kohm transimpedance and a 0.6uA input referred current noise, while operating with a photodiode capacitance of 0.6pF. A fully differential topology ensures good substrate and supply noise immunity. The amplifier, implemented in a triple metal, single poly, 14GHz f_T_max, 0.5um CMOS process, dissipates 225mW of which 110mW is consumed by the 50ohm output driver stage. The optimized on-chip inductors consume only 15% of the total area of 0.6mm^2.