H.-S. Philip Wong

_MG_8929 crop


Professor of Electrical Engineering

Willard R. and Inez Kerr Bell Professor in the School of Engineering



B.Sc. Hons. (1982) University of Hong Kong, M.S. (1983) State University of New York, Stony Brook, and Ph.D. (1988) Lehigh University. 



H.-S. Philip Wong is the Willard R. and Inez Kerr Bell Professor in the School of Engineering. He joined Stanford University as Professor of Electrical Engineering in September, 2004. From 1988 to 2004, he was with the IBM T.J. Watson Research Center


At IBM, he held various positions from Research Staff Member to Manager and Senior Manager. While he was Senior Manager, he had the responsibility of shaping and executing IBM’s strategy on nanoscale science and technology as well as exploratory silicon devices and semiconductor technology.


Professor Wong’s research aims at translating discoveries in science into practical technologies. His works have contributed to advancements in nanoscale science and technology, semiconductor technology, solid-state devices, and electronic imaging. His present research covers a broad range of topics including carbon electronics, 2D layered materials, wireless implantable biosensors, directed self-assembly, device modeling, brain-inspired computing, non-volatile memory, and monolithic 3D integration.


He is a Fellow of the IEEE. He served as the Editor-in-Chief of the IEEE Transactions on Nanotechnology (2005 – 2006), sub-committee Chair of the ISSCC (2003 – 2004), General Chair of the IEDM (2007), and is currently the Chair of the IEEE Executive Committee of the Symposia of VLSI Technology and Circuits. He is the faculty director of the Stanford Non-Volatile Memory Technology Research Initiative (NMTRI), and is the founding Faculty Co-Director of the Stanford SystemX Alliance – an industrial affiliate program focused on building systems.


An extended biography is here.



RESEARCH GROUP: Nanoelectronics and Nanotechnology (http://nano.stanford.edu)

Keywords: Nanotechnology, nanoelectronics, semiconductor technology, solid-state devices, Si CMOS, solid-state imaging.

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Education video on nanotechnology:

NSF Science Nation video on carbon nanotube nanosystems (produced by the National Science Foundation)

Carbon nanotube technology (funded by the National Science Foundation)

CNT at Stanford: Long, medium, short (funded by the National Science Foundation)




Some time ago, someone posed this question to me: “What comes after the computer chip?” Having spent most of my career on advancing semiconductor technology, which is the physical foundation of the computer chip, I find this question worth thinking about. So I wrote this blog on Slate.


21st century information technology (IT) must process, understand, classify, and organize vast amount of data in real-time. 21st century applications will be dominated by memory-centric computing operating on Tbytes of active data with little data locality. At the same time, massively redundant sensor arrays sampling the world around us will give humans the perception of additional “senses” blurring the boundary between biological, physical, and cyber worlds. Abundant-data processing, which comprises real-time big-data analytics and the processing of perceptual data in wearable devices, clearly demands computation efficiencies well beyond what can be achieved through business as usual.


The key elements of a scalable, fast, and energy-efficient computation platform that may provide another 1,000× in computing performance (energy-execution time product) for future computing workloads are: massive on-chip memory co-located with highly energy-efficient computation, enabled by monolithic 3D integration using ultra-dense and fine-grained massive connectivity. There will be multiple layers of analog and digital memories interleaved with computing logic, sensors, and application-specific devices.  We call this technology platform N3XT – Nanoengineered Computing Systems Technology. N3XT will support computing architectures that embrace sparsity, stochasticity, and device variability.


[N3XT: Nano-engineered Computing Systems Technology. Monolithic 3D integration of memory immersed in logic, connected by ultra-dense vertical connections. (graphics: Max Shulaker)]



For transistors it is important to have an atomically thin channel that enables gate length scaling while maintaining good carrier transport required for a high current drive. At the same time, parasitic resistance from the contacts and parasitic capacitance from the device structure must be minimized. Currently, we are working on the use of carbon nanotube (CNT) and two-dimensional layered materials (the transition metal dichalcogenide family of materials) as the atomically thin channel. We are also developing techniques to minimize the contact resistance and the parasitic capacitance. By building practical nanosystems of these emerging technologies, we learn how to solve fundamental device and materials science problems that have system-level impact.


[Aligned carbon nanotube growth (Albert Lin, Nishant Patil, Hong-Yu Chen, Luckshitha Liyanage)]

Picture1 [Carbon nanotube transistor array (Greg Pitner)]


 [A microprocessor made entirely out of carbon nanotubes with > 10,000 CNTs and > 2 billion carbon atoms (M. Shulaker et al.)]




I started doing research on memory devices around 2003. Research on memory had been rather “predictable” for many years until recently. It was predictable because the major advances for memory devices involved scaling down the physical dimensions of essentially the same device structure using basically the same materials. The situation has changed in the last decade. Memory devices are beginning to be difficult to scale down. But perhaps the most important change is that new applications and products (e.g. mobile phones, tablets, enterprise-scale disk storage) in the last decade are often enabled by advances in memory technology, in particular solid-state non-volatile memories.


Our research on memory devices broadly covers phase change memory (PCM), metal oxide resistive switching memory (RRAM), conductive bridge memory (CBRAM), and magnetic memory. We work on understanding the fundamental physics of these devices and develop models of how they work. We explore the use of various materials and device structures (e.g. 3D vertical RRAM) to achieve desired characteristics. We often utilize the unique properties of nanoscale materials such as carbon nanotube, graphene, and nanoparticles to help us gain understanding of the fundamental physics and scaling properties of memory devices. We are working on building memory systems that are monolithically integrated in 3D with logic computing elements.



 [3D Resistive Switching Random Access Memory (3D RRAM) (Hong-Yu Chen, Shimeng Yu, and collaborators at Peking University.)]


Picture6 [3D RRAM made with atomically thin (0.3 nm) plane electrode (Joon Sohn, Seunghyun Lee et al.)]


 [Nanoscale metal oxide RRAM fabricated by self-assembly patterning (Yi (Alice) Wu, He (Linda) Yi et al.)]


Picture4 Picture7 [Resistive switching Random Access Memory (RRAM) array (Joon Sohn)]




Interconnect wires are essential for electronic systems. We were the first to demonstrate GHz signaling through carbon nanotube and graphene interconnect wires. Currently we are exploring the use of graphene to improve copper wire reliability as well as copper wire resistance by reducing the thickness of the copper barrier layer by atomic layers of graphene.



Device model is the primary interface between device technology and circuit/system design. The models we develop help us understand the potential system-level benefits of the devices we do research on. Analysis and benchmarking against competing technologies is integral to our research programs. They provide the foundation and motivation for the experimental works. More detailed, physics-based models help us develop better devices based on a better understanding of the physics of operation. Models have been developed in the past for various devices: carbon nanotube transistor, III-V transistors, RRAM. These models are available on our group website under the model download link. We are active participants of the NSF-funded NCN-NEEDS for the development of compact models for emerging nanoelectronic devices.


 [Compact modeling of metal oxide RRAM (Haitong Li, Zizhen (Jane) Jiang, Shimeng Yu, Ximeng Guan et al.), Model available at: http://nano.stanford.edu/models.php]


Brain-Inspired Computing:

We are developing nanoscale electronic devices and circuits to emulate the functions of the synapses and neurons of the brain. The goal is to use nanoscale electronic devices to do information processing using algorithms and methods inspired by how the brain works. Currently, we are using a variety of new memory devices to perform gray-scale analog programming of the resistance values. These electronic emulations of the synapse are then connected in a neural network to process information and achieve simple learning behavior.


In the past few years, we have been able to emulate a variety of spike-timing dependent plasticity (STDP) behaviors of the biological synapse using these nanoscale electronic devices. Using larger arrays of electronic synapses, we study how device variations affect system performance. The stochastic nature of the switching process of these devices has a rich set of properties that may be utilized for many applications.


In the future, it may be possible to use these nanoscale electronic devices to study how the brain works, by interfacing these devices directly with biological entities.



NeuronCELL_Device_preview_round3 (1) [Nanoelectronic synapse (Duygu Kuzum, Rakesh Jeyasingh)]


 [Evolution of weights during learning in a 10 x 10 array of electronic synapses implemented by phase change memory (S. Burc Eryilmaz, D. Kuzum and IBM collaborators)]

Picture8 [Hyperdimensional computing using 3D RRAM (Haitong Li and collaborators at UC Berkeley and National Nano Device Laboratory, Taiwan)]



CHIC (CHip-in-Cell) – Autonomous bio-sensor:

In-situ detection of chemical changes in human body at the cellular level can bring enormous benefits in diagnosis and in therapeutic monitoring.  We are developing techniques to place micron-sized sensor chip inside each cell. It might revolutionize biochemical imaging by introducing the concept of replacing “passive” radiotracers with “active” IC chips.  This may open up an array of new biomedical applications that range from novel medical diagnostic and therapeutic tools that operate at single cell level to a novel class of autonomously operating intrabody nanobiosensors. These wireless bio-sensors can be used for autonomous, continuous-time, in vivo monitoring. Nanofabrication and integrated electronics are the key enabling technologies of this research.


Picture3 [Uptake of RFID by living cells (Xiaolin (Jasmine) Hu, Mimi Yang, Kokab Parizi)]



Self-Assembly for Device Fabrication:

We explore the use of directed self-assembly of diblock copolymers are for the fabrication of nanoelectronic devices. The focus is on device fabrication, understanding how directed self-assembly interacts with VLSI layout design, and developing design rules for the use of directed self-assembly for lithographic patterning for semiconductor devices and circuits.


In the past, we had successfully fabricated functional MOSFET and CMOS circuits using diblock copolymer as a patterning technique for features at the sub-20 nm scale. We have developed directed self-assembly (DSA) technology using small guiding templates with sizes that are comparable to the desired pitch to improve the DSA performance and to provide flexible controls on pitch, shape, and ordering of the self-assembly. These canonical templates, which are akin to the letters of the alphabet, are the most basic features essential to compose a device layout of complex circuits.


At the moment, we are focused on patterning tight pitch contact holes for VLSI circuits beyond the 10 nm node. Each template only generates one robust pattern consisting one or a few holes with certain size, shape and ordering. A canonical template database (the design rules) is being developed to cover all the essential patterns for device design. This is akin to composing the newspaper using only 26 letters of the alphabet. A complete VLSI circuit layout can be disassembled to a set of patterns that can be generated by the corresponding canonical templates (the alphabet set). On the other hand, designers can also design devices and circuits with modified or new layouts to best fit the DSA design rules for optimal patterning. The research combines experimental work with theoretical modeling. Modeling and simulation are employed to guide the experiments and the design automation development.


This is a field that crosses the boundaries of materials science, device design, circuit design, electronic design automation (EDA), and computer science.

.DSA Linda

 [Directed Self-Assembly of Random Logic Circuit Contact Holes at 14 nm node (He (Linda) Yi)]

DSA Stanford logo [Self-assembled Stanford logo (Li-Wen Chang)]

Smiley face grad student [Self-assembled Smiley Faces (Li-Wen Chang)]




The research projects have been / are supported in part by the National Science Foundation, NSF E3S S&T Center, DARPA, IARPA, STARnet SONIC, STARnet FAME, NCN-NEEDS, NSF Expedition on Computing (Visual Cortex on Silicon), Semiconductor Research Corporation, the Molecular Foundry (DoE LBNL), and the member companies of the Stanford SystemX Alliance, the Stanford Initiative for Nanoscale Materials and Processes (INMP), the Stanford Non-Volatile Memory Technology Research Initiative (NMTRI), as well as companies and philanthropic foundations.



We collaborate across campus with many faculty groups including: Prof. Subhasish Mitra, Prof. Simon Wong, Prof. Ada Poon, Prof. Roger Howe, Prof. Krishna Saraswat, Prof. Yoshio Nishi, Prof. Eric Pop, Prof. Zhenan Bao, Prof. Jonathan Fan, Prof. Michael McConnell, Dr. Demir Akin, and many others.


We actively collaborate with research groups worldwide including groups at U. Illinois at Urbana Champaign, UC Berkeley, UCSD, MIT, Arizona State University, Peking University (China), Tsinghua University (China), Soochow University (China), Hong Kong Polytechnic University, National Chiao Tung University (Taiwan), IMEC (Belgium), CEA-LETI (France), National Nano Device Laboratory (Taiwan), and IME A*STAR (Singapore).


We are part of the research centers led by UIUC, UCLA, UC Berkeley, Penn State, Notre Dame, and Purdue.


Examples of our research can be found in the publications and conference presentations listed below.


Selected Recent and Upcoming Conference Publications:


1.      R. Yang, H. Li, K.K.H. Smithe, T. R. Kim, K. Okabe, E. Pop, J. A. Fan, H.-S. P. Wong, “2D Molybdenum Disulfide (MoS2) Transistors Driving RRAMs with 1T1R Configuration,” International Electron Devices Meeting (IEDM), paper 19.5, December 4 – 6, San Francisco, 2017.

2.      Y. Shi, C. Pan, V. Chen, N. Raghavan, K.L. Pey, F.M. Puglisi, E. Pop, H.-S. P. Wong, M. Lanza, “Coexistence of volatile and non-volatile resistive switching in 2D h-BN based electronic synapses,” International Electron Devices Meeting (IEDM), paper 5.4, December 4 – 6, San Francisco, 2017.

3.      Z. Jiang, Z. Wang, X. Zheng, S. Fong, S. Qin, H.-Y. Chen, C. Ahn, J. Cao, Y. Nishi, and H.-S. P. Wong, “Microsecond Transient Thermal Behavior of HfOx-based Resistive Random Access Memory Using a Micro Thermal Stage (MTS),” IEEE International Electron Devices Meeting (IEDM), paper 21.3, December 5 – 7, San Francisco, 2016.

4.      H. Li, T.F. Wu, A. Rahimi. K.-S. Li, M. Rusch, C.-H. Lin, J.-L. Hsu, M.M. Sabry, S.B. Eryilmaz. J. Sohn, W.-C. Chiu, M.-C. Chen, T.-T. Wu, J.-M. Shieh, W.-K. Yeh, J. M. Rabaey, S. Mitra, and H.-S. P. Wong, “Hyperdimensional Computing with 3D VRRAM In-Memory Kernels: Device-Architecture Co-Design for Energy-Efficient, Error-Resilient Language Recognition,” IEEE International Electron Devices Meeting (IEDM), paper 16.1, December 5 – 7, San Francisco, 2016.

5.      L. Li, Z. Zhu, T. Wang, J.A. Currivan-Incorvia, A. Yoon, and H.-S. P. Wong, “BEOL Compatible Graphene/Cu with Improved Electromigration Lifetime for Future Interconnects,” IEEE International Electron Devices Meeting (IEDM), paper 9.5, December 5 – 7, San Francisco, 2016.

6.      C.-S. Lee, B. Cline, S. Sinha, G. Yeric, and H.-S. P. Wong, “32-bit Processor Core at 5-nm Technology: Analysis of Transistor and Interconnect Impact on VLSI System Performance,” IEEE International Electron Devices Meeting (IEDM), paper 28.3, December 5 – 7, San Francisco, 2016.

7.      H. Li, K.-S. Li, C.-H. Lin. J.-L. Hsu, W.-C. Chiu, M.-C. Chen, T.-T. Wu, J. Sohn, S. B. Eryilmaz, J.-M. Shieh, W.-K. Yeh, H.-S. P. Wong, “Four-Layer 3D Vertical RRAM Integrated with FinFET as a Versatile Computing Unit for Brain-Inspired Cognitive Information Processing,” Symp. VLSI Technology, Honolulu, HI, paper 20.2, June 13 – 17, 2016.

8.      M. M. Shulaker, G. Hills, M. Giachino, T.F. Wu, Z. Bao, H.-S. P. Wong, and S. Mitra, “Efficient Metallic Carbon Nanotube Removal for Highly-Scaled Technologies,” IEEE International Electron Devices Meeting (IEDM), paper 32.4, pp. 839 – 842, Washington, DC, December 7 – 9, 2015.

9.      X. Hu, W. Li, M.X. Yang, K. Aggarwal, A.S.Y. Poon, H.-S. P. Wong, “Mini-RFID Toward Implantable Cellular Sensors,” The 19th International Conference on Miniaturized Systems for Chemistry and Life Sciences (MicroTAS), Gyeongju, Korea, October 25 – 29, 2015.

10.   L. Li, X. Chen, C.-H. Wang, S. Lee, J. Cao, S. S. Roy, M. S. Arnold, and H.-S. P. Wong, “Cu Diffusion Barrier: Graphene Benchmarked to TaN for Ultimate Interconnect Scaling,” Symp. VLSI Technology, paper T8-4, pp. T122 – T123, Kyoto, Japan, June 15 – 19, 2015.

11.  H. Yi, J. Bekaert, R. Gronheid, G. Vandenberghe, K. Nafus, H.-S. P. Wong, “Experimental Study of Sub DSA resolution Assist Features (SDRAF),” SPIE Symposium on Advanced Lithography, Conferences on Alternative Lithographic Technologies VII, San Jose, CA, Paper 9423-50, 22 - 26 February 2015.    


Recent Invited Journal Articles:


1.      T.N. Theis and H.-S. P. Wong, “The End of Moore's Law: A New Beginning for Information Technology,”  invited paper, IEEE Computing in Science & Engineering, vol. 19, no. 2, pp. 41-50, Mar.-Apr. 2017.

2.      M. Shulaker, H.-S. P. Wong, S. Mitra, “Computing with Carbon Nanotubes,” IEEE Spectrum, Volume 53, Issue 7, pp. 26 – 52, 2016. Online version: http://spectrum.ieee.org/semiconductors/devices/how-well-put-a-carbon-nanotube-computer-in-your-hand, DOI: 10.1109/MSPEC.2016.7498155

3.      H.-S. P. Wong and S. Salahuddin, “Memory Leads the Way to Better Computing,” invited paper, Nature Nanotechnology, Vol. 10, pp. 191 – 194 (2015)

4.      D. Kuzum, S. Yu, H.-S. P. Wong, “Synaptic Electronics: Materials, Devices and Applications,” invited review, Nanotechnology, 24. 382001 doi:10.1088/0957-4484/24/38/382001, 2013.

5.      H.-S. P. Wong, H.-Y. Lee, S. Yu, Y.-S. Chen, Y. Wu, P.-S. Chen, B. Lee, F.T. Chen, M.-J. Tsai, “Metal Oxide RRAM,” invited paper, Proceedings of the IEEE, vol. 100, No. 6, pp. 1951 – 1970, June, 2012.

6.      H.-S. P. Wong, S. Raoux, S. Kim, J. Liang, J.P. Reifenberg, B. Rajendran, M. Asheghi, K.E. Goodson, “Phase Change Memory,” invited paper, Proceedings of the IEEE, Vol. 98, No. 12, pp. 2201 – 2227, December 2010.


Selected Recent Journal Articles:


1.      S.W. Fong, C.M. Neumann, and H.-S. P. Wong, “Phase-Change Memory – Toward a Storage-Class Memory,” IEEE Trans. Electron Devices, Volume: 64, Issue: 11, pp. 4374-4385 (2017).

2.      H. Li, T. F. Wu, S. Mitra, and H.-S. P. Wong, “Resistive RAM-Centric Computing: Design and Modeling Methodology,” IEEE Trans. Circuits and Systems I: Regular Papers, Vol. 64, No. 9, pp. 2263 – 2273 (2017).

3.      X. Hu, K. Aggarwal, M.X. Yang, K.B. Parizi, X. Xu, D. Akin, A. Poon, H.-S. P. Wong, “Micrometer-Scale Magnetic-Resonance-Coupled Radio-Frequency 305 Identification and Transceivers for Wireless Sensors in Cells,” Phys. Rev. Applied, 8: 014031 (2017).

4.      M.M. Shulaker, G. Hills, R. S. Park, R.T. Howe, K. Saraswat, H.-S. P. Wong, S. Mitra, “Three-dimensional Integration of Nanotechnologies for Computing and Data Storage on a Single Chip,” Nature, Vol. 547, pp. 74 – 78, 2017.

5.      Z. Wang, Z. Jiang, X. Zheng, S. Fong, H.-Y. Chen, H.-S. P. Wong, Y. Nishi, “Ultrafast Accelerated Retention Test Methodology for RRAM Using Micro Thermal Stage,” IEEE Electron Device Letters, vol. 38, no. 7, pp. 863-866, July 2017.

6.      P. Yao, H. Wu, B. Gao, S. B. Eryilmaz, X. Huang, W. Zhang, Q. Zhang, N. Deng, L. Shi, H.-S. P. Wong, H. Qian, “Face Classification using Electronic Synapses,” Nature Communications, 8:15199, May 12, 2017.

7.      S. B. Desai, S. R. Madhvapathy, A. R. Sachid, J. P. Llinas, Q. Wang, G.H. Ahn, G. Pitner, M.J. Kim, J. Bokor, C. Hu, H.-S. P. Wong, A. Javey, “MoS2 Transistors with 1-nanometere gate lengths,” Science, vol. 354, issue 6380, pp. 99 – 102, (2016).

8.      S. B. Eryilmaz, E. Neftci, S. Joshi, S. Kim, M. BrightSky, H. L. Lung, C. Lam, G. Cauwenberghs, H. S. P. Wong, "Training a Probabilistic Graphical Model With Resistive Switching Electronic Synapses," in IEEE Transactions on Electron Devices, vol. 63, issue 12, pp. 5004 - 5011, December, 2016.

9.      Z. Jiang, Y. Wu, S. Yu, L. Yang, K. Song, Z. Karim, H.-S. P. Wong, “A Compact Model for Metal–Oxide Resistive Random Access Memory With Experiment Verification,” IEEE Trans. Electron Devices, vol. 63, No. 5, pp. 1884 – 1892 (2016)

10.   L. Li, M. Engel, D. B. Farmer, S.-J. Han, H.-S. P. Wong, “High Performance p-Type Black Phosphorus Transistor with Scandium Contact,” ACS Nano, 10 (4), pp 4672–4677 (2016)

11.   R.S. Park, M.M. Shulaker, G. Hills, L.S. Liyanage, S. Lee, A. Tang, S. Mitra, H.-S. P. Wong, “Hysteresis in Carbon Nanotube Transistors: Measurement and Analysis of Trap Density, Energy Level, and Spatial Distribution,” ACS Nano, 10 (4), pp 4599–4608 (2016)

12.   S. Lee, A. Tang, S. Aloni, H.-S. P. Wong, “Statistical Study on the Schottky Barrier Reduction of Tunneling Contacts to CVD Synthesized MoS2,” Nano Lett.16 (1), pp 276–281 (2016)

13.   M.M. Sabry Aly, M. Gao, G. Hills, C.-S. Lee, G. Pitner, M.M. Shulaker, T.F. Wu, M. Asheghi, J. Bokor, F. Franchetti, K.E. Goodson, C. Kozyrakis, I. Markov, K. Olukotun, L. Pileggi, E. Pop, J. Rabaey, C. Re, H.-S. P. Wong, S. Mitra, "Energy-Efficient Abundant-Data Computing: The N3XT 1,000X," IEEE Computer, pp. 24 – 33, December 2015.

14.   C.S. Lee, E. Pop, A. Franklin, W. Haensch, H.-S. P. Wong, “A Compact Virtual-Source Model for Carbon Nanotube FETs in the Sub-10-nm Regime—Part II: Extrinsic Elements, Performance Assessment, and Design Optimization,” IEEE Trans. Electron Devices, vol. 62, no. 9, pp. 3070-3078 (2015).

15.   C. Ahn, S. W. Fong, Y. Kim, S. Lee A. Sood, C. M. Neumann, M. Asheghi, K.E. Goodson, E. Pop, H.-S. P. Wong, “Energy-Efficient Phase-Change Memory with Graphene as a Thermal Barrier,” Nano Letters, 15 (10), pp 6809–6814 2015.

16.   L. Li, X. Chen, C.-H. Wang, J. Cao, S. Lee, A. Tang, C. Ahn, S. S. Roy, M. S. Arnold, and H.-S. P. Wong, “Vertical and Lateral Copper Transport through Graphene Layers,” ACS Nano20159 (8), pp 8361–8367


Selected Publications Prior to Joining Stanford:


1.      T. Skotnicki, J. A. Hutchby, T.-J. King, H.-S. P. Wong, F. Beouff, “The Road to the End of CMOS Scaling,” invited paper, IEEE Circuits and Devices Magazine, pp. 16 – 26, 2005.

2.      H.-S. P. Wong, “Beyond the Conventional Transistor,” Solid State Electronics, vol. 49, pp. 755 – 762 (2005).

3.      J. Kedzierski, M. Ieong, T. Kanarsky, Y. Zhang, H.-S. P. Wong, “Fabrication of Metal Gated FinFETs Through Complete Gate Silicidation with Ni,” IEEE Trans. Electron Devices, vol. 51, No. 12, pp. 2115 – 2120 (2004).

4.      D.V. Singh, K.A. Jenkins, J. Appenzeller, D. Neumayer, A. Grill, H.-S. P. Wong, “Frequency Response of Top-Gated Carbon Nanotube Field-Effect Transistors,” IEEE Trans. Nanotechnology, vol. 3, no. 3, pp. 383 – 387 (2004).

5.      H. Shang, K.-L. Lee, P. Kozlowski, C.D’Emic, I. Babich, E. Sikorski, M. Ieong, H.-S. P. Wong, K. Guarini, and W. Haensch, “Self-Aligned n-Channel Germanium MOSFETs with a Thin Ge Oxynitride Gate Dielectric and Tungsten Gate,” IEEE Electron Device Letters, vol. 25, No. 3, pp. 135 – 137 (2004).

6.      J. Kedzierski, M. Ieong, E. Nowak, T.S. Kanarsky, Y. Zhang, R. Roy, D. Boyd, D. Fried, H.-S. P. Wong, “Extension and Source/Drain Design for High-Performance FinFET Devices,” IEEE Transactions on Electron Devices, vol. 50, No. 4, pp. 952 – 958, April, 2003.

7.      H. Shang, H. Okorn-Schmidt, J. Ott, P. Kozlowski, S. Steen, E.C. Jones, H.-S. P. Wong, W. Haensch, “Electrical Characterization of Germanium p-Channel MOSFETs,” IEEE Electron Device Letters, vol. 24, No. 4, pp. 242-244, April, 2003.

8.      X. Wang, H.-S. P. Wong, P. Oldiges and R.J. Miller, “Electrostatic Analysis of Carbon Nanotube Arrays,” 2003 IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Cambridge, MA, September 3 – 5, 2003.

9.      H.-S. P. Wong, J. Appenzeller, V. Derycke, R. Martel, S. Wind, Ph. Avouris, “Carbon Nanotube Field Effect Transistors – Fabrication, Device Physics, and Circuit Implications”, IEEE International Solid State Circuits Conference (ISSCC), p. 370 – 371, 2003.

10.   H.-S. P. Wong, “Beyond the Conventional Transistor”, invited paper, IBM J. Research & Development, March/May, pp. 133-168, 2002.

11.   J. Kedzierski, E. Nowak, Thomas Kanarsky, Y. Zhang, D. Boyd, R. Carruthers, C. Cabral, R. Amos, C. Lavoie, R. Roy, J. Newbury, E. Sullivan, J. Benedict, P. Saunders, K. Wong, D. Canaperi, M. Krishnan, K.-L. Lee, B. A. Rainey, D. Fried, P. Cottrell, H.-S. P. Wong, M. Ieong, W. Haensch, “Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation”, IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, pp. 247 – 250, 2002

12.   Z. Ren, S. Hedge, B. Doris, P. Oldiges, T. Kanarsky, O. Dokumaci, M. Ieong, E. C. Jones, H.-S. P. Wong, “An Experimental Study on Electrostatics and Transport Issues of Ultra-Thin Body SOI pMOSFETs”, IEEE Electron Device Letters, Vol. 23, No. 10, pp. 609-611, October, 2002.

13.   L.J. Huang, J.O.Chu, S. Goma, C.P. D’Emic, S. J. Koester, D. F. Canaperi, P. M. Mooney, S. A. Cordes,  J. L. Speidell, R. M. Anderson, H.-S. P. Wong, “Electron and Hole Mobility Enhancement in Strained Silicon-On-Insulator by Wafer Bonding,” IEEE Trans. Electron Devices, Vol. 49, pp. 1566 – 1571, September, 2002.

14.   B. Doris, M. Ieong, T. Kanarsky, Y. Zhang, R.A. Roy, O. Dokumaci, F.-F. Jamin, L. Shi , W. Natzle, H.-J. Huang, J. Mezzapelle, A. Mocuta, M. Gribelyuk , E.C. Jones, R.J. Miller, H.-S. P. Wong, and W. Haensch, “Extreme Scaling With Ultra-Thin Silicon Channel MOSFET’s (XFET)”, IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, pp. 267 – 270, 2002.

15.   K. Rim, E.P. Gusev, C. D’Emic, T. Kanarsky, H. Chen, J. Chu, J. Ott, K. Chan, D. Boyd, V. Mazzeo, B.H. Lee, A. Mocuta, J. Welser, S.L. Cohen, M. Ieong, and H.-S. P. Wong, “Mobility Enhancement in Strained Si NMOSFETs with HfO2 Gate Dielectrics”, Symp. VLSI Technology, pp. 12-13, June, 2002.

16.   R. Martel, H.-S. P. Wong, K. Chan, and Ph. Avouris, “Carbon Nanotube Field Effect Transistors for Logic Applications”, IEEE International Electron Devices Meeting (IEDM), Washington, D.C., pp. 159-162, 2001.

17.   D.J. Frank, R. H. Dennard, E. J. Nowak, P.M. Solomon, Y. Taur, H.-S. P. Wong, “Device Scaling Limits of Si MOSFETs and Their Application Dependencies”, invited paper, IEEE Proceedings, Special Issue on The Limits of Semiconductor Technology, pp. 259-288, March, 2001.

18.   H.-S. P. Wong, D.J. Frank, P.M. Solomon, H.-J. Wann, J. Welser, “Nanoscale CMOS'', IEEE Proceedings, invited paper, Special Issue on Quantum Devices and Applications, pp. 537-570, April, 1999.


Recent and Upcoming Invited Presentations:


1.      H.-S. P. Wong, “Reaching for the N3XT 1,000× of Computing Energy Efficiency,” invited plenary paper, Device Research Conference (DRC), Santa Barbara, CA, June 24 – 27, 2018.

2.      H.-S. P. Wong, “Reaching for the N3XT 1,000× of Computing Energy Efficiency,” invited plenary paper, Semiconductor Integrated Circuit Technology Workshop (SICTW) at West Lake, Zhejiang University, Hangzhou, China, November 6 – 9, 2017.

3.      H.-S. P. Wong, “On to the Next Fifty Years – Guideposts from the Past Fifty Years,” invited plenary paper, Semiconductor Integrated Circuit Technology Workshop (SICTW) at West Lake, Zhejiang University, Hangzhou, China, November 6 – 9, 2017.

4.      H.-S. P. Wong, “The N3XT Technology for Brain-Inspired Computing,” invited paper, IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), San Francisco, CA, October 16 – 19, 2017.

5.      H. Li, T. F. Wu, S. Mitra, H.-S. P. Wong, “Device-Architecture Co-Design for Hyperdimensional Computing with 3D Vertical Resistive Switching Random Access Memory (3D VRRAM),” invited paper, International Symposium on VLSI Technology, Systems and Applications (2017 VLSI-TSA), Hsinchu, Taiwan, 24- 27 April, 2017.



H.-S. P. Wong and D. Akinwande, “Carbon Nanotube and Graphene Device Physics,” Cambridge University Press, 2011.  (ISBN-13: 9780521519052). Available at Amazon.com.


CNT book cover




EE 21N Freshman Seminar (new class since Autumn, 2006, next offering: Winter 2018) – “What is Nanotechnology?”).

EE 320 (evolved from EE 218, new in 2008/09, Spring 2009, next offerings: Spring 2019, in alternate years) “Nanoelectronics” (There is no required textbook for this course) – Prerequisite EE222, EE216 and knowledge of solid state physics,  Recommended: EE 223, 228, or 316.

             (slides for 1st lecture of EE 218 back in Autumn 2005) (rather old, kept here for historical reasons, as a time capsule)


EE 316 (Winter) “Advanced VLSI Devices”

EE 309 (new class since Spring, 2006, offered in alternate years, next class: Autumn 2017) “Semiconductor Memory Devices and Technology” (There is no required textbook for this course) – Prerequisite: EE 216. Preferred: EE 316, EE 313, EE 311

EE 392B (Spring, 2005, not offered in the near future) “Introduction to Image Sensors and Digital Cameras” (with Prof. Abbas El Gamal)


EE 310 Seminar slides:

October 5, 2004. Download here. (rather old, kept here for historical reasons, as a time capsule)



H.-S. Philip Wong

Department of Electrical Engineering and Stanford SystemX Alliance,

Paul G. Allen 312X

420 Via Palou,

Stanford University, Stanford, CA 94305-4075

Email: hspwong AT stanford DOT edu

Phone: +1-650-725-0982


Administrative Assistant: Fely Barrera

Email:  fbarrera AT Stanford DOT edu

Phone: +1-650-723-1349


Last modified:

November 21, 2017