H.-S. Philip Wong

_MG_8929 crop

 

Professor of Electrical Engineering

Willard R. and Inez Kerr Bell Professor in the School of Engineering

 

Education:

B.Sc. Hons. (1982) University of Hong Kong, M.S. (1983) State University of New York, Stony Brook, and Ph.D. (1988) Lehigh University. 

 

Biography:

H.-S. Philip Wong is the Willard R. and Inez Kerr Bell Professor in the School of Engineering. He received the B.Sc. (Hons.) in 1982 from the University of Hong Kong, the M.S. in 1983 from the State University of New York at Stony Brook, and the Ph.D. in 1988 from Lehigh University, all in electrical engineering. He joined the IBM T. J. Watson Research Center, Yorktown Heights, New York, in 1988. In September, 2004, he joined Stanford University as Professor of Electrical Engineering.

 

While at IBM, he worked on CCD and CMOS image sensors, double-gate/multi-gate MOSFET, device simulations for advanced/novel MOSFET, strained silicon, wafer bonding, ultra-thin body SOI, extremely short gate FET, germanium MOSFET, carbon nanotube FET, and phase change memory. He held various positions from Research Staff Member to Manager and Senior Manager. While he was Senior Manager, he had the responsibility of shaping and executing IBM’s strategy on nanoscale science and technology as well as exploratory silicon devices and semiconductor technology.

 

Professor Wong’s research aims at translating discoveries in science into practical technologies. His work contributed to the advancements in nanoscale science and technology, semiconductor technology, solid-state devices, and electronic imaging. He explores the use of nano-materials, nanofabrication techniques, and novel device concepts for nanoelectronics systems. Novel devices often enable new concepts in circuit and system designs. His research also includes explorations into circuits and systems that are device-driven.

 

Currently, his research covers a broad range of topics including carbon electronics, 2D layered materials, wireless implantable biosensors, self-assembly, nanoelectromechanical relays, device modeling, brain-inspired computing, and non-volatile memory devices such as phase change memory and metal oxide resistance change memory.

 

He is a Fellow of the IEEE and served on the IEEE Electron Devices Society (EDS) as elected AdCom member from 2001 – 2006. He served on the IEDM committee from 1998 to 2007 and was the Technical Program Chair in 2006 and General Chair in 2007. He served on the ISSCC program committee from 1998 – 2004, and was the Chair of the Image Sensors, Displays, and MEMS subcommittee from 2003-2004. Currently, he is the Executive Committee Chair (NAE) of the Symposia of VLSI Technology and Circuits. He was the Editor-in-Chief of the IEEE Transactions on Nanotechnology in 2005 – 2006. He is a Distinguished Lecturer of the IEEE Electron Devices Society (since 1999) and Solid-State Circuit Society (2005 – 2007).

 

His academic appointments include the Chair of Excellence of the French Nanosciences Foundation, Guest Professor of Peking University, Honorary Professor of the Institute of Microelectronics of the Chinese Academy of Sciences, visiting Chair Professor of Nanoelectronics of the Hong Kong Polytechnic University, and the Honorary Doctorate degree from the Institut Polytechnique de Grenoble, France.

 

 

RESEARCH GROUP: Nanoelectronics and Nanotechnology (http://nano.stanford.edu)

Keywords: Nanotechnology, nanoelectronics, semiconductor technology, solid-state devices, Si CMOS, solid-state imaging.

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Education video on nanotechnology:

Carbon nanotube technology (funded by the National Science Foundation)

CNT at Stanford: Long, medium, short (funded by the  National Science Foundation)

 

RESEARCH AREAS:

 

Some time ago, someone posed this question to me: “What comes after the computer chip?” Having spent most of my career on advancing semiconductor technology, which is the physical foundation of the computer chip, I find this question worth thinking about. So I wrote this blog on Slate.

 

There is still plenty of room at the bottom for electronic devices. The three pillars of electronic systems are equally important: logic, memory, communication. For logic device (the “switch”) that performs the computation, there is the need to reduce energy consumption while maximizing speed and device density. We work on advancing transistor technology as well as device technology that are not based on transistors. Memory has become the enabler for new applications. Access to data has become one of the most important aspects of information technology today. New memory devices may bring about a completely different memory and storage hierarchy from what has been in use for the past several decades. As information technology become pervasive in society and ubiquitous in our lives, the desire for always-on, always-available, embedded everywhere, and human-centric information systems may call for a different computation paradigm. The device and fabrication technologies developed will have applications far beyond information technology. The research directions we have chosen reflect these observations.

 

Logic:

For transistors it is important to have an atomically thin channel that enables gate length scaling while maintaining good carrier transport required for a high current drive. At the same time, parasitic resistance from the contacts and parasitic capacitance from the device structure must be minimized. Currently, we are working on the use of carbon nanotube (CNT) and two-dimensional layered materials (the transition metal dichalcogenide family of materials) as the atomically thin channel. We are also developing techniques to minimize the contact resistance and the parasitic capacitance. By building practical systems of these emerging technologies, we learn how to solve fundamental device and materials science problems that have system-level impact.

 

[Aligned carbon nanotube growth (Albert Lin, Nishant Patil, Hong-Yu Chen, Luckshitha Liyanage)]

 

 [A microprocessor made entirely out of carbon nanotubes with > 10,000 CNTs and > 2 billion carbon atoms (M. Shulaker et al.)]

 

Devices other than transistors may offer unique properties for certain applications. An example is the nanoelectromechanical (NEM) relay. It has zero off-state leakage current (for low energy consumption) and can be used in various applications where only moderate speed is required.

 

NEM relay SEM [Nanoelectromechanical (NEM) relay (Soogine Chong, Roozbeh Parsa)]

 

[Paper Clip Nanoelectromechanical (NEM) relay (Dr. Daesung Lee)]

 

[NEM relay integrated with Si CMOS (Soogine Chong)]

 

Memory:

I started doing research on memory devices around 2003. Research on memory had been rather “predictable” for many years until recently. It was predictable because the major advances for memory devices involved scaling down the physical dimensions of essentially the same device structure using basically the same materials. The situation has changed in the last decade. Memory devices are beginning to be difficult to scale down. But perhaps the most important change is that new applications and products (e.g. mobile phones, tablets, enterprise-scale disk storage) in the last decade are often enabled by advances in memory technology, in particular solid-state non-volatile memories.

 

Our research on memory devices focuses on phase change memory (PCM) and metal oxide resistive switching memory (RRAM). We work on understanding the fundamental physics of these devices and develop models of how they work. We explore the use of various materials and device structures (e.g. 3D vertical RRAM) to achieve desired characteristics. We often utilize the unique properties of nanoscale materials such as carbon nanotube, graphene, and nanoparticles to help us gain understanding of the fundamental physics and scaling properties of memory devices.

 

[48 nm x 48 nm cross-point memory (Byoungil Lee)]

 

CNT PCM[Cross-point phase change memory using carbon nanotube electrode (Jiale Liang)]

 

CNT RRAM[Cross-point metal oxide RRAM using carbon nanotube electrode (Yi (Alice) Wu)]

 

 [3D vertical RRAM (Hong-Yu Chen, Shimeng Yu et al.)]

 

 [Nanoscale metal oxide RRAM fabricated by self-assembly patterning (Yi (Alice) Wu, He (Linda) Yi et al.)]

 

 

Communication:

Interconnect wires are essential for electronic systems. We were the first to demonstrate GHz signaling through carbon nanotube and graphene interconnect wires. Currently we are exploring the use of graphene for improving interconnect wire reliability.

 

Modeling:

Device model is the primary interface between device technology and circuit/system design. The models we develop help us understand the potential system-level benefits of the devices we do research on. Analysis and benchmarking against competing technologies is integral to our research programs. They provide the foundation and motivation for the experimental works. More detailed, physics-based models help us develop better devices based on a better understanding of the physics of operation. Models have been developed in the past for various devices: carbon nanotube transistor, III-V transistors, RRAM. These models are available on our group website under the model download link. We are active participants of the NSF-funded NCN-NEEDS for the development of compact models for emerging nanoelectronic devices.

 

 [Compact modeling of metal oxide RRAM (Zizhen (Jane) Jiang, Shimeng Yu, Ximeng Guan et al.)]

 [Monte Carlo modeling of RRAM (Shimeng Yu, Ximeng Guan)]

 

Brain-Inspired Computing:

We are developing nanoscale electronic devices and circuits to emulate the functions of the synapses and neurons of the brain. The goal is to use nanoscale electronic devices to do information processing using algorithms and methods inspired by how the brain works. Currently, we are using phase change memory and metal oxide RRAM to perform gray-scale analog programming of the resistance values. These electronic emulations of the synapse are then connected in a neural network to process information and achieve simple learning behavior.

 

In the past few years, we have been able to emulate a variety of spike-timing dependent plasticity (STDP) behaviors of the biological synapse using these nanoscale electronic devices. Using larger arrays of electronic synapses, we study how device variations affect system performance. The stochastic nature of the switching process of these devices has a rich set of properties that may be utilized for many applications.

 

In the future, it may be possible to use these nanoscale electronic devices to study how the brain works, by interfacing these devices directly with biological entities.

 

 

NeuronCELL_Device_preview_round3 (1) [Nanoelectronic synapse (Duygu Kuzum, Rakesh Jeyasingh)]

 

 [Evolution of weights during learning in a 10 x 10 array of electronic synapses implemented by phase change memory (S. Burc Eryilmaz, D. Kuzum et al.)]

 

 

CHIC (CHip-in-Cell) – Autonomous bio-sensor:

In-situ detection of chemical changes in human body at the cellular level can bring enormous benefits in diagnosis and in therapeutic monitoring.  We are developing techniques to place micron-sized sensor chip inside each cell. It might revolutionize biochemical imaging by introducing the concept of replacing “passive” radiotracers with “active” IC chips.  This may open up an array of new biomedical applications that range from novel medical diagnostic and therapeutic tools that operate at single cell level to a novel class of autonomously operating intrabody nanobiosensors. These wireless bio-sensors can be used for autonomous, continuous-time, in vivo monitoring. Nanofabrication and integrated electronics are the key enabling technologies of this research.

 

 [Delivery of 3D multilayer µTags into living cells (Lisa Chen, Kokab Parizi et al.)]

 

 

Self-Assembly for Device Fabrication:

We explore the use of directed self-assembly of diblock copolymers are for the fabrication of nanoelectronic devices. The focus is on device fabrication, understanding how directed self-assembly interacts with VLSI layout design, and developing design rules for the use of directed self-assembly for lithographic patterning for semiconductor devices and circuits.

 

In the past, we had successfully fabricated functional MOSFET and CMOS circuits using diblock copolymer as a patterning technique for features at the sub-20 nm scale. We have developed directed self-assembly (DSA) technology using small guiding templates with sizes that are comparable to the desired pitch to improve the DSA performance and to provide flexible controls on pitch, shape, and ordering of the self-assembly. These canonical templates, which are akin to the letters of the alphabet, are the most basic features essential to compose a device layout of complex circuits.

 

At the moment, we are focused on patterning tight pitch contact holes for VLSI circuits beyond the 10 nm node. Each template only generates one robust pattern consisting one or a few holes with certain size, shape and ordering. A canonical template database (the design rules) is being developed to cover all the essential patterns for device design. This is akin to composing the newspaper using only 26 letters of the alphabet. A complete VLSI circuit layout can be disassembled to a set of patterns that can be generated by the corresponding canonical templates (the alphabet set). On the other hand, designers can also design devices and circuits with modified or new layouts to best fit the DSA design rules for optimal patterning. The research combines experimental work with theoretical modeling. Modeling and simulation are employed to guide the experiments and the design automation development.

 

This is a field that crosses the boundaries of materials science, device design, circuit design, electronic design automation (EDA), and computer science.

.DSA Linda

 [Directed Self-Assembly of Random Logic Circuit Contact Holes at 14 nm node (He (Linda) Yi)]

DSA Stanford logo [Self-assembled Stanford logo (Li-Wen Chang)]

Smiley face grad student [Self-assembled Smiley Faces (Li-Wen Chang)]

 

 

Sponsors:

The research projects are supported in part by the National Science Foundation, DARPA, IARPA, STARnet SONIC, STARnet FAME, NCN-NEEDS, NSF Expedition on Computing (Visual Cortex on Silicon), Semiconductor Research Corporation, the Molecular Foundry (DoE LBNL), and the member companies of the Stanford Center for Integrated Systems (CIS), the Stanford Initiative for Nanoscale Materials and Processes (INMP), the Stanford Non-Volatile Memory Technology Research Initiative (NMTRI), as well as companies and philanthropic foundations.

 

Collaborators:

We collaborate across campus with may faculty groups including: Prof. Subhasish Mitra, Prof. Simon Wong, Prof. Ada Poon, Prof. Roger Howe, Prof. Krishna Saraswat, Prof. Yoshio Nishi, Prof. Eric Pop, Prof. Zhenan Bao, Prof. Michael McConnell, and many others.

 

We actively collaborate with research groups worldwide including groups at U. Illinois at Urbana Champaign, UC Berkeley, UCSD, Peking University (China), Tsinghua University (China), National Chiao Tung University (Taiwan), IMEC (Belgium), and IME A*STAR (Singapore).

 

We are part of the research centers led by UIUC, UCLA, UC Berkeley, Penn State, and Purdue.

 

Examples of our research can be found in the publications and conference presentations listed below.

 

Selected Recent and Upcoming Conference Publications:

 

1.      M. Shulaker, T. Wu, A. Pal, K. Saraswat, H.-S. P. Wong, S. Mitra, “Monolithic 3D Integration of Logic and Memory: Carbon Nanotube FETs, Resistive RAM, and Silicon FETs,” IEEE International Electron Devices Meeting (IEDM), December 15 – 17, San Francisco, 2014.

2.      M. Shulaker, G. Pitner, G. Hills, M. Giachino, H.-S. P. Wong, S. Mitra, “High-Performance Carbon Nanotube Transistors,” IEEE International Electron Devices Meeting (IEDM), December 15 – 17, San Francisco, 2014.

3.      L. Zhao, Z. Jiang, H.-Y. Chen, J. Sohn, K. Okabe, B. Magyari-Köpe, H.-S. P. Wong, Y. Nishi, “Ultrathin (~2nm) HfOx as the Fundamental Resistive Switching Element: Thickness Scaling Limit, Stack Engineering and 3D Integration,” IEEE International Electron Devices Meeting (IEDM), December 15 – 17, San Francisco, 2014.

4.      J. H. Engel, S. B. Eryilmaz, S. Kim, M. BrightSky, C. Lam, B. A. Olshausen, and H.-S. P. Wong, “Capacity Optimization of Emerging Memory Systems: A Shannon-Inspired Approach to Device Characterization,” IEEE International Electron Devices Meeting (IEDM), December 15 – 17, San Francisco, 2014.

5.      J. Sohn, S. Lee, Z. Jiang, H.-Y. Chen, H.-S. P. Wong, “Atomically Thin Graphene Plane Electrode for 3D RRAM,” IEEE International Electron Devices Meeting (IEDM), paper 5.3, December 15 – 17, San Francisco, 2014.

6.      Z. Jiang, S. Yu, Y. Wu, J. H. Engel, X. Guan, H.-S. P. Wong, “Verilog-A Compact Model for Oxide-based Resistive Random Access Memory (RRAM),” International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), paper 3-3, Yokohama, Japan, September 9 – 11, 2014

7.      M.C. Tung, H. Yi, T. Iwama, N. Laachi, K. T. Delaney, G.H. Fredrickson, and H.-S. P. Wong, “Defect Reduction of Peanut-Shaped Direct Self-Assembly using Hompolymer,” 58th International Conference on Electron, Ion, and Photon Beam Technology and Nanofabrication (EIPBN), Washington, D.C., May 27 – May 30, 2014.

8.      M. M. Shulaker, K. Saraswat, H.-S. P. Wong, S. Mitra, “Monolithic Three-Dimensional Integration of Carbon Nanotube FETs with Silicon CMOS,” Symp. VLSI Technology, paper T19.4, Honolulu, HI, June 9 – 13, 2014.

9.      H.-Y. Chen, B. Gao, H. Li, R. Liu, P. Huang. Z. Chen, B. Chen, F. Zhang, L. Zhao, Z. Jiang, L. Liu, X. Liu J. Kang, S. Yu, Y. Nishi, H.-S. P. Wong, “Towards High-Speed, Write-Disturb Tolerant 3D Vertical RRAM Arrays,” Symp. VLSI Technology, Honolulu, HI, paper T22.2, June 9 – 13, 2014.

10.   C. Ahn, Z. Jiang, C.-S. Lee, H.-Y. Chen, J. Liang, L. S. Liyanage, and H.-S. P. Wong, “A 1TnR Array Architecture using a One-Dimensional Selection Device,” Symp. VLSI Technology, paper T15.4, Honolulu, HI, June 9 – 13, 2014.

11.   Y. Wu, H. Yi, Z. Zhang, Z. Jiang, J. Sohn, S. Wong, H.-S. P. Wong, “First Demonstration of RRAM Patterned by Block Copolymer Self-Assembly,” IEEE International Electron Devices Meeting (IEDM), paper 20.8, December 9 – 11, Washington, D.C., 2013.

12.   Y. Deng, H.-Y. Chen, B. Gao, S. Yu, S.-C. Wu, L. Zhao, B. Chen, Z. Jiang, T.-H. Hou, Y. Nishi, J.F. Kang, and H.-S. P. Wong, “Design and Optimization Methodology for 3D RRAM Arrays,” IEEE International Electron Devices Meeting (IEDM), paper 25.7, December 9 – 11, Washington, D.C., 2013.

13.   H. Wei, M. Shulaker, H.-S. P. Wong, and S. Mitra, “Monolithic Three-Dimensional Integration of Carbon Nanotube FET Complementary Logic Circuits,” IEEE International Electron Devices Meeting (IEDM), paper 19.7, December 9 – 11, Washington, D.C., 2013.

14.   S. B. Eryilmaz, D. Kuzum, R. G. D. Jeyasingh, S. Kim, M. BrightSky, C. Lam and H.-S. P. Wong, “Experimental Demonstration of Array-level Learning with Phase Change Synaptic Devices,” IEEE International Electron Devices Meeting (IEDM), paper 25.5, December 9 – 11, Washington, D.C., 2013.

15.   S. Yu, H.-Y. Chen, Y. Deng, B. Gao, Z. Jiang, J. Kang, H.-S. P. Wong, “3D Vertical RRAM – Scaling Limit Analysis and Demonstration of 3D Array Operation,” Symp. VLSI Technology, paper T11-4, pp. T158 – 159, Kyoto, Japan, June 11 – 14, 2013.

16.   H. Yi, H.-S. P. Wong, “Block Copolymer Directed Self-Assembly Two-Hole Pattern inside Peanut-Shaped Templates,” 57th International Conference on Electron, Ion, and Photon Beam Technology and Nanofabrication (EIPBN), paper 10B-05, Nashville, TN, May 28 – May 31, 2013.

     

Recent Invited Journal Articles:

 

1.      D. Kuzum, S. Yu, H.-S. P. Wong, “Synaptic Electronics: Materials, Devices and Applications,” invited review, Nanotechnology, 24. 382001 doi:10.1088/0957-4484/24/38/382001, 2013.

2.      M. Caldwell, R.G.D. Jeyasingh, H.-S. P. Wong, D. Milliron, “Nanoscale Phase Change Memory Materials,” invited feature article Nanoscale, vol. 4, pp. 4382 – 4392 (2012). DOI: 10.1039/C2NR30541K

3.      J. Zhang, A. Lin, N. Patil, H. Wei, L. Wei, H.-S. P. Wong, S. Mitra, “Robust Digital VLSI using Carbon Nanotubes,” invited keynote paper, IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 31, No. 4, pp. 453 – 471, 2012. DOI: 10.1109/TCAD.2012.2187527 

4.      H.-S. P. Wong, H.-Y. Lee, S. Yu, Y.-S. Chen, Y. Wu, P.-S. Chen, B. Lee, F.T. Chen, M.-J. Tsai, “Metal Oxide RRAM,” invited paper, Proceedings of the IEEE, vol. 100, No. 6, pp. 1951 – 1970, June, 2012.

5.      H.-S. P. Wong, S. Raoux, S. Kim, J. Liang, J.P. Reifenberg, B. Rajendran, M. Asheghi, K.E. Goodson, “Phase Change Memory,” invited paper, Proceedings of the IEEE, Vol. 98, No. 12, pp. 2201 – 2227, December 2010.

 

Selected Recent Journal Articles:

 

1.      L.Y. Chen†, B. C-K Tee†, A.L. Chortos, G. Schwartz, V. Tse, D. Lipomi, H.-S. P. Wong, M.V. McConnell, Z. Bao, “Continuous Wireless Pressure Monitoring and Mapping with Ultra-Small Passive Sensors for Health Monitoring and Critical Care,” Nature Communications, 2014. †=equal contribution.

2.      S. B. Eryilmaz, D. Kuzum, R. Jeyasingh, S. Kim, M. Brightsky, C. Lam, H.-S. P. Wong, “Brain-like associative learning using a nanoscale non-volatile phase change synaptic device array,” Frontiers in Neuroscience, 8:205 (2014). doi: 10.3389/fnins.2014.00205

3.      B. Gao, Y. Bi, H.-Y. Chen, R. Liu, P. Huang, B. Chen, L. Liu, X. Liu, S. Yu, H.-S. P. Wong, J. Kang, “Ultra-Low Energy Three-Dimensional Oxide-Based Electronic Synapses for Implementation of Robust High Accuracy Neuromorphic Computation Systems,” ACS Nano, accepted for publication 2014.

4.      M.M. Shulaker, J. van Rethy, T.F. Wu, L.S. Liyanage, H. Wei, Z. Li, E. Pop, G. Gielen, H.-S. P. Wong, and S. Mitra, “Carbon Nanotube Circuit Integration Up to Sub-20 nm Channel Lengths,” ACS Nano, Vol. 8, No. 4, pp. 3434 – 3443, (2014). DOI: 10.1021/nn406301r

5.      L. S. Liyanage, X. Xu, G. Pitner, Z. Bao, and H.-S. P. Wong, “VLSI-Compatible Carbon Nanotube Doping Technique with Low Work-function Metal Oxides,” Nano Letters, 14 (4), pp 1884–1890 (2014). DOI: 10.1021/nl404654j

6.      M. M. Shulaker, J. Van Rethy, G. Hills, H. Wei, H.-Y. Chen, G. Gielen, H.-S. P. Wong, S. Mitra, “Sensor-to-Digital Interface Built Entirely With Carbon Nanotube FETs,” IEEE J. Solid-State Circuits, vol. 49, No. 1, pp. 190 – 201 (2014).

7.      S. Yu, B. Gao, Z. Fang, H. Yu, J. Kang, H.-S. P. Wong, “Stochastic Learning in Oxide Binary Synaptic Device for Neuromorphic Computing,” Frontiers in Neuroscience, vol. 7, article 186, pp. 1 – 9, October 31, 2013. doi: 10.3389/fnins.2013.00186

8.      H.-Y. Chen, S. Yu, B. Gao, R. Liu, Z. Jiang, Y, Deng, B. Chen, J. Kang, H.-S. P. Wong, “Experimental Study of Plane Electrode Thickness Scaling for 3D Vertical Resistive Random Access Memory,” Nanotechnology, 24, 465201, 2013. doi:10.1088/0957-4484/24/46/465201

9.      M. Shulaker, G. Hills, N. Patil, H. Wei, H.-Y. Chen, H.-S. P. Wong, S. Mitra, “Carbon Nanotube Computer,” Nature, vol. 501, pp. 256 – 530, 2013. doi:10.1038/nature12502

10.   L. Y. Chen†, K. B. Parizi†, H. Kosuge, K. M. Milaninia, M. V. McConnell, H.-S. P. Wong, A. S.Y. Poon, “Mass fabrication and delivery of 3D multilayer µTags into living cells,” Scientific Reports, 3. 02295, July 2013. doi:10.1038/srep02295, †=equal contribution.

11.   S. Yu, H.-Y. Chen, B. Gao, J. F. Kang, H.-S. P. Wong, “A HfOx Based Vertical Resistive Switching Random Access Memory Suitable for Bit-Cost-Effective 3D Cross-Point Architecture,” ACS Nano, 7 (3), pp 2320–2325, 2013.

12.   Z. Zhang, Y. Wu, H.-S. P. Wong, S.S. Wong, “Nanometer-scale HfOx RRAM,” IEEE Electron Device Letters, vol. 34, No.8, pp. 1005 – 1007, 2013.

13.   S. Yu, B. Gao, Z. Fang, H. Yu, J. Kang, H.-S. P. Wong, “Stochastic Learning in Oxide Binary Synaptic Device for Neuromorphic Computing,” Advanced Materials, Volume 25, Issue 12, pages 1774–1779, March 25, 2013.

14.   H. Tian, H.-Y. Chen, B. Gao, S. Yu, J. Liang, Y. Yang, D. Xie, J. Kang, T.-L Ren, Y. Zhang, and H.-S. P. Wong, “Monitoring Oxygen Movement by Raman Spectroscopy of Resistive Random Access Memory with a Graphene-Inserted Electrode,” Nano Letters, 13 (2), pp 651–657, 2013. DOI: 10.1021/nl304246d

15.   J. Luo, L. Wei, C.-S. Lee, A. D. Franklin, X. Guan, E. Pop, D. A. Antoniadis, H.-S. P. Wong, “A Compact Model for Carbon Nanotube Field-Effect Transistors Including Non-Idealities and Calibrated with Experimental Data Down to 9 nm Gate Length,” IEEE Trans. Electron Device, vol. 60, no. 6, pp. 1834 – 1843, June 2013.

16.   J. Liang, S. Yeh, S.S. Wong, H.-S. P. Wong, “Effect of Wordline/Bitline Scaling on the Performance, Energy Consumption, and Reliability of Cross-point Memory Array,” ACM Journal on Emerging Technologies in Computing Systems (JETC), Vol. 9, No. 1, Article 9, pp. 9:1 – 9:14, February, 2013

 

Selected Publications Prior to Joining Stanford:

 

1.      T. Skotnicki, J. A. Hutchby, T.-J. King, H.-S. P. Wong, F. Beouff, “The Road to the End of CMOS Scaling,” invited paper, IEEE Circuits and Devices Magazine, pp. 16 – 26, 2005.

2.      H.-S. P. Wong, “Beyond the Conventional Transistor,” Solid State Electronics, vol. 49, pp. 755 – 762 (2005).

3.      J. Kedzierski, M. Ieong, T. Kanarsky, Y. Zhang, H.-S. P. Wong, “Fabrication of Metal Gated FinFETs Through Complete Gate Silicidation with Ni,” IEEE Trans. Electron Devices, vol. 51, No. 12, pp. 2115 – 2120 (2004).

4.      D.V. Singh, K.A. Jenkins, J. Appenzeller, D. Neumayer, A. Grill, H.-S. P. Wong, “Frequency Response of Top-Gated Carbon Nanotube Field-Effect Transistors,” IEEE Trans. Nanotechnology, vol. 3, no. 3, pp. 383 – 387 (2004).

5.      H. Shang, K.-L. Lee, P. Kozlowski, C.D’Emic, I. Babich, E. Sikorski, M. Ieong, H.-S. P. Wong, K. Guarini, and W. Haensch, “Self-Aligned n-Channel Germanium MOSFETs with a Thin Ge Oxynitride Gate Dielectric and Tungsten Gate,” IEEE Electron Device Letters, vol. 25, No. 3, pp. 135 – 137 (2004).

6.      J. Kedzierski, M. Ieong, E. Nowak, T.S. Kanarsky, Y. Zhang, R. Roy, D. Boyd, D. Fried, H.-S. P. Wong, “Extension and Source/Drain Design for High-Performance FinFET Devices,” IEEE Transactions on Electron Devices, vol. 50, No. 4, pp. 952 – 958, April, 2003.

7.      H. Shang, H. Okorn-Schmidt, J. Ott, P. Kozlowski, S. Steen, E.C. Jones, H.-S. P. Wong, W. Haensch, “Electrical Characterization of Germanium p-Channel MOSFETs,” IEEE Electron Device Letters, vol. 24, No. 4, pp. 242-244, April, 2003.

8.      X. Wang, H.-S. P. Wong, P. Oldiges and R.J. Miller, “Electrostatic Analysis of Carbon Nanotube Arrays,” 2003 IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Cambridge, MA, September 3 – 5, 2003.

9.      H.-S. P. Wong, J. Appenzeller, V. Derycke, R. Martel, S. Wind, Ph. Avouris, “Carbon Nanotube Field Effect Transistors – Fabrication, Device Physics, and Circuit Implications”, IEEE International Solid State Circuits Conference (ISSCC), p. 370 – 371, 2003.

10.   H.-S. P. Wong, “Beyond the Conventional Transistor”, invited paper, IBM J. Research & Development, March/May, pp. 133-168, 2002.

11.   J. Kedzierski, E. Nowak, Thomas Kanarsky, Y. Zhang, D. Boyd, R. Carruthers, C. Cabral, R. Amos, C. Lavoie, R. Roy, J. Newbury, E. Sullivan, J. Benedict, P. Saunders, K. Wong, D. Canaperi, M. Krishnan, K.-L. Lee, B. A. Rainey, D. Fried, P. Cottrell, H.-S. P. Wong, M. Ieong, W. Haensch, “Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation”, IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, pp. 247 – 250, 2002

12.   Z. Ren, S. Hedge, B. Doris, P. Oldiges, T. Kanarsky, O. Dokumaci, M. Ieong, E. C. Jones, H.-S. P. Wong, “An Experimental Study on Electrostatics and Transport Issues of Ultra-Thin Body SOI pMOSFETs”, IEEE Electron Device Letters, Vol. 23, No. 10, pp. 609-611, October, 2002.

13.   L.J. Huang, J.O.Chu, S. Goma, C.P. D’Emic, S. J. Koester, D. F. Canaperi, P. M. Mooney, S. A. Cordes,  J. L. Speidell, R. M. Anderson, H.-S. P. Wong, “Electron and Hole Mobility Enhancement in Strained Silicon-On-Insulator by Wafer Bonding,” IEEE Trans. Electron Devices, Vol. 49, pp. 1566 – 1571, September, 2002.

14.   B. Doris, M. Ieong, T. Kanarsky, Y. Zhang, R.A. Roy, O. Dokumaci, F.-F. Jamin, L. Shi , W. Natzle, H.-J. Huang, J. Mezzapelle, A. Mocuta, M. Gribelyuk , E.C. Jones, R.J. Miller, H.-S. P. Wong, and W. Haensch, “Extreme Scaling With Ultra-Thin Silicon Channel MOSFET’s (XFET)”, IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, pp. 267 – 270, 2002.

15.   K. Rim, E.P. Gusev, C. D’Emic, T. Kanarsky, H. Chen, J. Chu, J. Ott, K. Chan, D. Boyd, V. Mazzeo, B.H. Lee, A. Mocuta, J. Welser, S.L. Cohen, M. Ieong, and H.-S. P. Wong, “Mobility Enhancement in Strained Si NMOSFETs with HfO2 Gate Dielectrics”, Symp. VLSI Technology, pp. 12-13, June, 2002.

16.   R. Martel, H.-S. P. Wong, K. Chan, and Ph. Avouris, “Carbon Nanotube Field Effect Transistors for Logic Applications”, IEEE International Electron Devices Meeting (IEDM), Washington, D.C., pp. 159-162, 2001.

17.   D.J. Frank, R. H. Dennard, E. J. Nowak, P.M. Solomon, Y. Taur, H.-S. P. Wong, “Device Scaling Limits of Si MOSFETs and Their Application Dependencies”, invited paper, IEEE Proceedings, Special Issue on The Limits of Semiconductor Technology, pp. 259-288, March, 2001.

18.   H.-S. P. Wong, D.J. Frank, P.M. Solomon, H.-J. Wann, J. Welser, “Nanoscale CMOS'', IEEE Proceedings, invited paper, Special Issue on Quantum Devices and Applications, pp. 537-570, April, 1999.

 

Recent and Upcoming Invited Presentations:

 

1.      L. S. Liyanage, M. Shulaker, X. Xu, G. Pitner,  R. Park, K. Saraswat, Z. Bao, S. Mitra, H.-S. P. Wong, “VLSI Compatible n-Type Carbon Nanotube Doping Technique and Monolithic Integration of CNTFETs with Silicon CMOS,” invited paper, Materials Research Society Fall Meeting, Symposium MM: “Carbon Nanotubes—Synthesis, Properties, Functionalization and Applications”, Boston, MA, November 30 - December 5, 2014,

2.      M. S. Ebrahimi, G. Hills, M. M. Sabry, M. M. Shulaker, H. Wei, T. F. Wu, S. Mitra, H.-S. P. Wong, “Monolithic 3D Integration Advances and Challenges: From Technology to System Levels”, invited paper, IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Millbrae, CA, October 6 – 10, 2014.

3.      H.-Y. Chen, M. Shulaker, S. Yu, H. Wei, B. Gao, J. Kang, S. Mitra, and H.-S. P. Wong, “Monolithic 3D Integration of Logic and Memory,” invited paper, 16th ACM/IEEE System Level Interconnect Prediction (SLIP), San Francisco, CA, June 1, 2014.

4.      M. Shulaker, G. Hills, N. Patil, H. Wei, H. Y. Chen, H. S. P. Wong, and S. Mitra,  “Carbon Nanotube Computer: Transforming Scientific Discoveries into Working System,” invited paper, 225th Electrochemical Society Meeting, paper M4-1188, Orlando, FL, May 11 – 15, 2014.

5.      M. Shulaker, G. Hills, H. Wei, H-Y. Chen, N. Patil, H.-S. P. Wong, S. Mitra, “Advancements with Carbon Nanotube Digital Systems,” invited paper, IEEE International Interconnect Technology Conference (IITC), paper 2.4, May 20-23, 2014.

6.      J.F. Kang, B.Gao, Y.J. Bi, B. Chen, and X.Y. Liu, S.M. Yu, H-Y. Chen, and H.-S. P. Wong, “TMO-based Memristive Devices and Application for Neuromorphic Systems,” invited paper, 13th International Conference on Modern Materials and Technologies (CIMTEC), 6th Forum on New Materials, Montecantini Terme, Italy, June 15 – 20, 2014.

7.      J.F. Kang, B. Gao, B. Chen, P. Huang, F.F. Zhang, X.Y. Liu, H-Y. Chen, Z. Jiang, H.-S. P. Wong, S.M. Yu, “Scaling and Operation Characteristics of HfOx Based Vertical RRAM for Cost-Effective 3D Cross-Point Architecture,” invited paper, IEEE Symposium on Circuits and Systems (ISCAS), Melbourne, Australia, June 1 – 5, 2014.

8.      S. Yu, D. Kuzum, and H.-S. P. Wong, “Design considerations of synaptic device for neuromorphic computing,” invited paper, IEEE Symposium on Circuits and Systems (ISCAS), Melbourne, Australia, June 1 – 5, 2014.

9.      S. Yu, Y. Deng, B. Gao, P. Huang, B. Chen, X. Y. Liu, J. F. Kang, H.-Y. Chen, Z. Jiang, and H.-S. P. Wong, “Design guidelines for 3D RRAM cross-point architecture,” invited paper, IEEE Symposium on Circuits and Systems (ISCAS), Melbourne, Australia, June 1 – 5, 2014.

10.   M. Shulaker, G. Hills, H. Wei, H-Y. Chen, N. Patil, H.-S. P. Wong, S. Mitra, “Carbon Nanotube Computer,” invited paper, Materials Research Society Spring Meeting (MRS), paper MM9.02, April 21 – 25, 2014.

11.   S. Yu, Y. Wu, H-Y. Chen, Z. Jiang, J. Sohn, H.-S. P. Wong, “Metal–Oxide-Based Resistive Switching Memory (RRAM): Modeling, Scaling, and 3D integration,” invited paper, Materials Research Society Spring Meeting (MRS), paper BB10.02, April 21 – 25, 2014.

12.   H.-S. P. Wong, “Building Complex Systems Using Nanomaterials,” invited paper, 2014 Foresight Technical Conference, Palo Alto, CA, February 7 – 9, 2014.

 

Book:

H.-S. P. Wong and D. Akinwande, “Carbon Nanotube and Graphene Device Physics,” Cambridge University Press, 2011.  (ISBN-13: 9780521519052). Available at Amazon.com.

 

CNT book cover

 

 

Classes:

EE 21N Freshman Seminar (new class since Autumn, 2006, next offering: Winter 2015) – “What is Nanotechnology?”).

EE 320 (evolved from EE 218, new in 2008/09, Spring 2009, next offerings: Spring 2017, in alternate years) “Nanoelectronics” (There is no required textbook for this course) – Prerequisite EE222, EE216 and knowledge of solid state physics,  Recommended: EE 223, 228, or 316.

             (slides for 1st lecture of EE 218 back in Autumn 2005) (rather old, kept here for historical reasons, as a time capsule)

 

EE 316 (Winter) “Advanced VLSI Devices”

EE 310 (Winter) (with Prof. Krishna Saraswat and Prof. Yoshio Nishi) “EE Seminar” (not offered in 2014)

EE 309 (new class since Spring, 2006, next offering: Fall 2016, offered in alternate years) “Semiconductor Memory Devices and Technology” (There is no required textbook for this course) – Prerequisite: EE 216. Preferred: EE 316, EE 313, EE 311

EE 392B (Spring, 2005, not offered in the near future) “Introduction to Image Sensors and Digital Cameras” (with Prof. Abbas El Gamal)

 

EE 310 Seminar slides:

October 5, 2004. Download here. (rather old, kept here for historical reasons, as a time capsule)

 

Contacts: 

H.-S. Philip Wong

Department of Electrical Engineering and Center for Integrated Systems,

Paul G. Allen 312X

420 Via Palou,

Stanford University, Stanford, CA 94305-4075

Email: hspwong AT stanford DOT edu

Phone: +1-650-725-0982

 

Administrative Assistant: Fely Barrera

Email: fely.barrera AT Stanford DOT edu

Phone: +1-650-723-1349

 

Last modified:

September 6, 2014