AWARDS AND HONORS:

Fellow, ACM, 2014, “for contributions to the design and testing of robust computing systems.”


A. Richard Newton Technical Impact Award in Electronic Design Automation, to honor an outstanding technical contribution, as evidenced by a paper published at least 10 years before the presentation of the award, 2014. Citation: "For a major breakthrough in test response compaction that is key to cost-effective manufacturing of high-quality electronic systems."


Jack Raper Award for Outstanding Technology-Directions Paper, 2013 IEEE International Solid-State Circuits Conference, 2014. (Students: Max Shulaker, Gage Hills)


Honor for Ph.D. student: European Design Automation Association (EDAA) Outstanding Dissertation Award won by Dr. Yanjing Li, 2014.


Honor for Ph.D. student: 2013 National Award for Outstanding Self-financed Chinese Students Studying Abroad won by Dr. Hai Wei, 2014.


Invited Professor, Ecole Polytechnique Federale De Lausanne (EPFL), 2014.


Erasmus Mundus Distinguished Lecturer on Embedded Computer Systems, Technical University of Kaiserslautern, Germany, 2014.


Fellow, IEEE, 2013, “for contributions to design and test of robust integrated circuits.”


Kavli Foundation Fellow, United States National Academy of Sciences, 2013.


World Economic Forum Young Scientist, 2013.


Best in Session Award, Semiconductor Research Corporation (SRC) TechCon, 2012. (Student: David Lin)


Chambers Faculty Scholar, Stanford School of Engineering, 2011.


Best Paper Award, 2010 IEEE VLSI Test Symposium, 2011. (Student: Yanjing Li)


Best Student Paper Award, 2010 IEEE International Test Conference, 2011. (Students: Ted Hong, Yanjing Li, David Lin, Diana Mui, Ziyad Abdel Khaleq, Sung-Boem Park)


Honor for PhD. student: ACM SIGDA Outstanding Dissertation Award won by Dr. Nishant Patil, 2011.


Honored by multiple graduating seniors and “Terman Award” recipients as a Stanford professor who had been important to them during their time at Stanford, 2009, 2010, 2011.


Research Highlight by the ACM, Special Invited Feature Article in the Communications of the ACM, 2010.


Research highlight to the United States Congress by the National Science Foundation, 2009.


Invited member, DARPA Information Science and Technology Board (ISAT), 2009.


Okawa Foundation Research Grant, The Okawa Foundation for Information and Telecommunications, Japan, 2009.


Invited Participant, National Academy of Engineering, US Frontiers of Engineering Symposium, 2009.


Best Student Paper Award, 2008 Symposium VLSI Technology, 2009.(Student: Nishant Patil)


Presidential Early Career Award for Scientists and Engineers (PECASE), "the highest honor bestowed by the United States government on outstanding scientists and engineers beginning their independent careers," 2008.


Best Paper Award, IEEE/ACM Design Automation Conference, 2008. (Student: Sung-Boem Park)


ACM SIGDA Outstanding New Faculty Award, 2008.


CAREER Award, National Science Foundation, 2007.


IBM Faculty Award, 2006, 2007, 2008.


Terman Fellow, 2006.


Top 10 papers at the IEEE International Test Conference, 2002, 2006.


IEEE Circuits and Systems Society Donald O. Pederson Outstanding Paper Award recognizing the Best Paper published in the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2005.


Best Paper Award, Intel Design and Test Technology Conference, 2005 for the paper "Built-In Soft Error Resilience Structures."


S. Seshu Scholar Lecturer, Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, 2005.


Divisional Recognition award, Intel Corp., “For Breakthrough Soft Error Protection Technology for Flip-flops,” 2005.


Intel Achievement Award, Intel’s highest corporate honor, “For the development and deployment of a breakthrough test compression technology that improved scan test cost by an order of magnitude,” 2004. (Pictures: http://www.stanford.edu/~subh/iaa.html).


Best panel award, IEEE VLSI Test Symposium, 2002, 2006.

 

PLENARY / INVITED TALKS:

Invited tutorial speaker, IEEE International Reliability Physics Symposium, Monterey, CA, 2015

Invited tutorial speaker, IEEE Asia and South Pacific Design Automation Conference, Tokyo, Japan, 2015.

Invited speaker, IEEE International Symposium on Integrated Circuits, Singapore, 2014
Invited panelist, Symposium on Emerging Electronics Trends, Montreux, Switzerland, 2014 

Invited panelist, Supercomputing, New Orleans, LA, 2014

Invited speaker, IEEE/ACM Workshop on Variability Modeling and Characterization, San Jose, CA, 2014

Invited panelist, CTO Forum, San Francisco, CA, 2014
Invited speaker, Global Forum on Nanoelectronic Manufacturing: From Materials to Systems Mumbai, India, 2014
Invited speaker, International Conference on Mirco and Nano Engineering, Lausanne, Switzerland, 2014
Invited speaker, IEEE Custom Integrated Circuits Conference, San Jose, CA, 2014
Keynote speaker, Symposium on Integrated Circuits and System Design (SBCCI), Aracaju, Brazil, 2014
Invited speaker, IEEE International Interconnect Technology Conference, San Jose, CA, 2014
Invited speaker, International Symposium on VLSI Technology, Systems and Applications and International Symposium on VLSI Design, Automation and Test, Hsinchu, Taiwan, 2014
Invited speaker, International Symposium on Physical Design, Sonoma County, CA, 2014
Invited speaker, IEEE/ACM Design Automation and Test in Europe, Dresden, Germany, 2014
Keynote speaker, IEEE International Symposium on Quality Electronic Design, Santa Clara, CA, 2014
Invited speaker, American Physical Society Meeting, Denver, CO, 2014
Invited speaker, Xilinx Emerging Technology Symposium, San Jose, CA, 2014
Invited speaker, IEEE Asia and South Pacific Design Automation Conference, Singapore, 2014
Keynote speaker, IEEE International Conference on VLSI Design, Mumbai, India, 2014
Invited speaker, "The Next Transistor Workshop," Radcliffe Institute, Harvard University, 2013
Invited speaker, IEEE International Symposium on Low-Power Electronics and Design, Beijing, China, 2013
IEEE/ACM Design Automation Conference, Austin, TX, 2013
Invited tutorial speaker, IEEE European Test Symposium, Avignon, France, 2013
International Workshop on Design with Nanoscale Functionality-Enhanced Devices, Lausanne, Switzerland, 2013
IEEE/ACM Design Automation and Test in Europe, Grenoble, France, 2013
Keynote speaker, Semicon China, Symposium on Metrology, Reliability and Testing, Shanghai, China, 2013
Japan Science and Technology Agency International Symposium on Dependable VLSI Systems, Tokyo, Japan, 2012
ITRS Workshop on Emerging Research Devices, Bordeaux, France, 2012
Dagstuhl Seminar on Reliability, Germany, 2012
CMOS ET Conference, Vancouver, Canada, 2012
IEEE Nuclear and Space Radiation Effects Conference (NSREC), Miami, FL, 2012
IEEE Intl. Symp. On-line Testing, Sitges, Spain, 2012
Invited tutorial speaker, IEEE/ACM Intl. Symp. Computer Architecture, Portland, OR, 2012
Invited panelist, IEEE/ACM Design Automation Conference, San Francisco, CA, 2012
Invited panelist, European Test Symposium, Annecy, France, 2012
Test Spring School, Talloires, France, 2012
CAS-FEST, Seoul, Korea, 2012
Intel Platform Validation Engineering Day, Portland, Oregon, 2012
Invited panelist, GOMACTECH, Las Vegas, NV, 2012
Invited panelist, IEEE/ACM Design Automation and Test in Europe, Dresden, Germany, 2012
Keynote speaker, Synthesis And System Integration of Mixed Information technologies (SASIMI), Japan, 2012
ISSCC Forum on Robust VLSI, ISSCC, San Francisco, CA, 2012
IEEE/ACM Asia and South Pacific Design Automation Conference, Sydney, Australia, 2012
IEEE VLSI Design Conference, Hyderabad, India, 2012
IEEE/ACM International Conference CAD, San Jose, CA, 2011
Allerton Conference, Allerton, IL, 2011
IEEE International Test Conference, Anaheim, CA, 2011
New Frontiers plenary session, SRC TechCon, Austin, TX, 2011
IFIP 10.4 WG, Hardware Issues in Dependable and Secure Computing, Taiwan, 2011
Invited panelist, IEEE/ACM Design Automation Conference, San Diego, CA, 2011
Cadence Design Systems Speaker Series, Cadence, San Jose, 2011
Design-for-Excellence in Electronics, New York University Abu Dhabi, New York, 2011
Invited panelist, Synopsys Users Group (SNUG), San Jose, 2011
Nanosystems and Variability, EPFL, Switzerland, 2011
D2T Symposium, University of Tokyo, 2011
IEEE/ACM Design Automation and Test in Europe, 2011
Keynote speaker, IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, 2011
IEEE International Symposium on Embedded System Design, 2010
IEEE Indicon, 2010
IEEE CAS JETCAS FEST, 2010
Microelectronics Reliability and Qualification Workshop, 2010
IEEE/ACM International Conference on Computer-Aided Design, 2010
Keynote Speaker, IEEE VLSI-SoC Conference, 2010
Intel Haifa Symposium, 2010
IEEE/ACM Design Automation Conference, 2010
D2T Symposium on Dependable VLSI, University of Tokyo, 2010
IEEE Latin American Test Workshop, 2010
ACM Timing Issues in the Specification and Synthesis of Digital Systems, 2010
IEEE/ACM Design Automation and Test in Europe, 2010
International Conference on VLSI Design, 2010
LSI Test and Verification Symposium, University of Tokyo, 2009
Dinner Speaker, IEEE International Workshop on Logic synthesis, 2009
International Test Conference, 2009
Symposium on Dependable VLSI, Japan Society for the Promotion of Science (JSPS), 2009
Invited panelist, Symposium VLSI Circuits, 2009
IEEE/ACM Design Automation Conference, 2009
Design Automation and Test in Europe, 2009
Distinguished Speaker Series, IEEE Council of EDA (CEDA), 2009
IEEE/ACM Asia South Pacific Design Automation Conference, 2009
Keynote speaker, EDA Forum, Dresden, Germany, 2008
Plenary speaker, IBM P = ac^2 Conference, 2008
Special Symposium on LSI Testing and Verification, University of Tokyo, Japan, 2008
Foundations of Nano (FNANO), 2008
New Frontiers in Nanoscale Electronics, EPFL, Switzerland 2008
IEEE/ACM Design Automation and Test in Europe, 2008
IEEE International On-line Test Symposium, 2008
IEEE International Reliability Physics Symposium, 2008
IEEE International Symposium on Quality Electronic Design, 2008
IEEE International Integrated Reliability Workshop (IRW), 2008
IEEE International Test Conf., 2007
IEEE VLSI Design and Test Symposium (India), 2007
IEEE International On-line Test Symposium, 2007
Invited panelist, IEEE VLSI Test Symposium, 2007
New Frontiers in Nanoscale Electronics, EPFL, Switzerland 2007
IEEE MPSoC 2007
IEEE International Conference on Integrated Circuit Design Technology, 2007
Invited panelist, IEEE International On-line Test Symposium, 2006
Invited panelist, IEEE VLSI Test Symposium, 2006
Cisco High Availability Workshop, 2006
IFIP / IEEE SOC-VLSI Conference, 2006
IEEE International Workshop on High Performance Computing Reliability Issues, 2006
Invited panelist, IEEE/ACM International Conf. Computer-Aided Design, 2005
IEEE/ACM Design Automation Conference, 2005
IEEE VLSI Test Symposium, 2005
IEEE International Conf. Computer Design, 2003
Invited panelist, IEEE Design & Test of Computers Roundtable, 2002
NASA/DoD International Conf. Evolvable Hardware, 2002 

 

INVITED PRESENTATIONS AT ACADEMIC INSTITUTIONS AND INDUSTRY

Agilent Technologies; AMD; ARM; Cadence; CalTech; Carnegie-Mellon University; Compaq Tandem Laboratories; Cray; DARPA; Die Products Consortium; EPFL, Switzerland; Freescale; Google; Hewlett-Packard; Imperial College, London; IBM; Indian Statistical Institute, Calcutta, India; Infineon Technologies; Institute of Defense Analysis; Intel Corporation; Massachusetts Institute of Technology; Microsoft Research; Nara Institute of Science and Technology, Japan; NXP, Eindhoven, NL; nVidia,Santa Clara; Oregon State University, Princeton University; Stanford University; Synopsys; Texas A&M University; Texas Instruments; University of California, Berkeley; University of Erlangen, Germany; University of Freiburg, Germany; University of Illinois at Urbana-Champaign; University of Michigan, Ann Arbor; University of Minnesota, University of Stuttgart, Germany; University of Texas at Austin; University of Tokyo, Japan; University of Wisconsin-Madison, and several others.