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Stanford University

Ze Yuan

Ze Yuan

Biography

Ze Yuan was born in Beijing, China. He received B. Eng degree in Microelectronic Engineering from Tsinghua University, Beijing, China in 2009, M. Sc. degree in Electrical Engineering from Stanford University, Stanford, CA in 2011, where he is now working towards doctoral degree in Electrical Engineering, with minor in Material Science and Engineering. During his undergraduate and graduate studies, he was an intern at SuVolta, Inc., Applied Materials Inc., Agilent Technologies Inc., Microsoft Research Asia, and IBM China. He has published more than 20 papers on III-V CMOS technology, silicon photonics, nanoscale MOS device simulation and modeling. His research interests are in the physics and technology of semiconductor devices. He is an active reviewer for IEEE Transactions on Electron Device and IEEE Electron Device Letters.

Ze Yuan was a recipient of several awards, including Stanford Graduate Fellowship, Pan-Wen Yuan Scholarship, and Oustanding Overseas Chinese Student Scholarship. Ze Yuan is a student member of IEEE starting from January 2009. He was a former member of the IEEE Electron Device Society's Tsinghua Chapter, chair of the Student Association of Science and Technology.

 

Education

2011-present

PhD Candidate
Advisor: Prof. Krishna Saraswat
Thesis topic:
Antimonide-based III-V CMOS Technology
Department of Electrical Engineering, Stanford University, CA, USA

2009-2011

Master of Science in Electrical Engineering
GPA: 4.07/4.00

Department of Electrical Engineering, Stanford University, CA, USA

2005-2009

Bachelor of Engineering, Outstanding Graduate with Highest Honor
GPA: 92.5/100 Rank: 1/62
Department of Microelectronics and Nanoelectronics, Tsinghua University, Beijing

2007

Undergraduate Exchange Program
GPA: 4.00/4.00

Department of Electrical and Electronic Engineering, University of Hong Kong, Hong Kong

Research

Center for Integrated Systems, Stanford University


Design of III-V CMOS Transistors February 2010 to present
  • High-performance III-V lattice-matched heterostructure MOSFET simulation
  • Optimized the design of the heterostructure based III-V MOSFETs for ION/IOFF, Sub-threshold Slope (SS), Band-to-band Tunneling (BTBT), DIBL; specifications relevant for logic design.
  • Experimental demonstration of Antimonides-based III-V pMOSFET outperforming Germanium.
  • Tight-binding simulation and study of bandstructure effects in III-V CMOS transistors
  • Epitaxial design of antimonide-based heterostructure with InGaSb as the single channel material for both n- and p-channel MOSFETs
  • Process development, including surface passivation, source/drain implantation and contact engineering for antimonide-based NMOSFETs
Integration of Ge, III-Vs on silicon using Rapid-Melt-Growth (RMG) August 2010 to present
  • First demonstration of GeOI by RMG (Rapid Melt Growth) technique with scaled in fin dimensions.
  • Study on the key differences between Si and III-V FinFETs designs, which suggests III-V-OI architecture is optimal for III-Vs for the control of the degraded SCEs and process variability.
  • Comprehensive material study on crystalline quality of InAs / GaSb integrated on silicon using RMG
  • Experimental demonstration of InAs-OI NMOS and GaSb-OI PMOS on silicon for III-V CMOS
Tunnel FET Design and Simulation March 2010 to June 2010
  • Device simulation and optimization of Tunnel FET with different electrostatic designs.
  • Presented analytical model for the electrostatic design of generic Tunnel FETs from the isolation of electric-field perspective.
  • Proposed effective-mass engineering based on directional tunneling for high on-current Tunnel FETs.
Agilent Technologies Inc., Santa Rosa CA June 2011 to September 2011
Comprehensive Study of Base Design in InP HBTs
  • Bandstructure and mobility calculation of strained GaAsSb to investigate strain-enhanced hole transport in base layer of InP HBTs.
  • Design of both composition and doping grading for GaAsSb base to maintain high current gain, while reducing sheet resistance and boosting frequency performance.
  • Epitaxial growth design for the study of strained GaAsSb base, lattice/transport/band-energies characterization of strained films.
  • Simulation of the combined effects of composition/doping grading on the device performance in InP HBTs.

Institute of Microelectronics, Tsinghua University

 

Quantum Transport

January 2008 to August 2008

  • Handled Non-Equilibrium Green Function¡¯s Technique, and Quantum Transmit Boundary Method;
  • Proposed formalism to represent non-local Quantum effects induced by change in potential for NEGF and boosted performance of convergence for general NEGF problems;

Compact Modeling of DG-FET

October 2008 to July 2009

  • Reviewed potential approach and analytical models unifying partially and fully depleted modes;
  • Presented analytical solution to 2D Poisson¡¯s equation for Short-Channel-Effects based on Generalized Scale Length analysis;
  • Proposed quantum mechanical model DG MOSFETs, using Variational and Perturbation methods;
  • Short-channel modelling of DG MOSFET with Voltage-Doping Transformation;

Publication

Ze Yuan, Aneesh Nainani , Yun Sun , J. Y. Jason Lin , Piero A. Pianetta , Krishna C. Saraswat, ¡°Schottky barrier height reduction for metal/n-GaSb contact by inserting TiO2 interfacial layer with low tunneling resistance,¡± Applied Physics Letters, Vol. 98, 18, May 2011.

Ze Yuan, Aneesh Nainani, Brian R. Bennett, J. Brad Boos, Mario G. Ancona and Krishna Saraswat, "Amelioration of interface-state response using band engineering in III-V quantum-well MOSFETs," Applied Physics Letters, Vol. 100, 14, 2012.

Ze Yuan, Aneesh Nainani, J.-Y. Jason Lin, Brian R. Bennett, J. Brad Boos, Mario G. Ancona and K. C. Saraswat, "Fermi-level pinning at metal/GaSb interface and demonstration of InGaSb channel Schottky pMOSFETs with metal S/D," 2011 69th Device Research Conference, Santa Barbara, USA June 2011.

Ze Yuan, Aneesh Nainani, Ximeng Guan, H-S. Philip Wong and Krishna Saraswat, ¡°Tight-binding Study of G-L Bandstructure Engineering for Ballistic III-V nMOSFETs,¡± 2011 International Conference on Simulation of Semiconductor Processes and Devices, September, Osaka, Japan, 2011.

Ze Yuan, Aneesh Nainani, Brian. R. Bennett, J. Brad Boos, Mario G. Ancona and Krishna C. Saraswat, ¡°Heterostructure Design and Demonstration of InGaSb Channel III-V CMOS Transistors,¡± 2011 International Semiconductor Device Research Symposium, Washington D.C. USA, Decebember, 2011.

Ze Yuan, Aneesh Nainani, Archana Kumar, Ximeng Guan, Brian R. Bennett, J. Brad Boos, Mario G. Ancona and K. C. Saraswat, "InGaSb: single channel solution for III-V CMOS," VLSI Technology, 2012 Symposium on, June, 2012.

Ze Yuan, Aneesh Nainani, Archana Kumar, Ximeng Guan, Brian R. Bennett, J. Brad Boos, Mario G. Ancona, Jame Champlain and Krishna Saraswat, "Heterostructure design for InGaSb-based single channel III-V CMOS," Transactions on Electron Devices, IEEE, in preparation.

Ze Yuan, Chien-Yu Chen, Archana Kumar, Peter Griffin, James Plummer and Krishna C. Saraswat, " Co-integration of InAs-OI, GaSb-OI on silicon substrate for III-V CMOS using rapid-melt-growth," Transactions on Electron Devices, IEEE, in preparation.

Archana Kumar, Ze Yuan, Aneesh Nainani, Krishna C. Saraswat, " Variability study of III-V FinFETs: bulk versus III-V-OI FinFETs," Transactions on Electron Devices, IEEE, in preparation.

Krishna C. Saraswat, J.-Y. Jason Lin, Arunanshu Roy, Bin Yang and Ze Yuan, "Schottky Barrier Height Engineering for Low-resistance contacts to Ge and III-V Devices," 222th Electrochemical Society Meeting, Hawaii USA, September, 2012.

Aneesh Nainani, Ze Yuan, Archana Kumar, J. Brad Boos, Brian R. Bennett and Krishna Saraswat, ¡°III-Sb MOSFETs: Opportunities and Challenges,¡± 221st Electrochemical Society Meeting, Seattle, May 2012.

Aneesh Nainani, Yun Sun, Toshifumi Irisawa, Ze Yuan, et al., ¡°Device quality Sb-based compound semiconductor surface: A comparative study of chemical cleaning,¡± Journal of Applied Physics 109, 114908, 2011.

Aneesh Nainani, Ze Yuan, Tejas Krishnamohan, Yoshio Nishi, Krishna C. Saraswat, Brian R. Bennett, J. Brad Boos, Mario G. Ancona, ¡°InxGa1-xSb channel pMOSFETs: Effect of strain and heterostructure design,¡± Journal of Applied Physics, 110, 014503, 2011.

Aneesh Nainani, Toshifumi Irisawa, Ze Yuan, Yoshio Nishi, Krishna C. Saraswat, ¡°Optimization of the Al2O3/GaSb interface and a high mobility GaSb p-MOSFET,¡± Transcations on Electron Devices, IEEE, 58, 10, 2011.

Aneesh Naninani, Toshifumi Irisawa, Ze Yuan, Yun Sun, Tejas Krishnamohan, M. Reason, Brian R. Benett, J. Brad Boos, Mario Ancona, Yoshio Nishi, Krishna C. Saraswat, ¡°Development of high-k dielectric for Antimonides and a sub 350 degree C III-V pMOSFET outperforming Ge, ¡± IEEE International Electron Devices Meeting, San Francisco, US, 2010.

Aneesh Nainani, Ze Yuan, Tejas Krishnamohan, Krishna Saraswat, ¡°Optimal Design of III-V Heterostructure MOSFETs,¡± 15th International Conference on Simulation of Semiconductor Processes and Devices, Bologna, Italy, 2010.

D. Nam, D. Sukhdeo, A. Roy, K. Balram, S.-L. Cheng, K. C.-Y. Huang, Ze Yuan, M. Brongersma, Y. Nishi, D. Miller, K. Saraswat, ¡°Strained germanium thin film membrane on silicon substrate for optoelectronics,¡± Optics Express, 19, 25866, 2011.

Ze Yuan, Meng Li, Zhiping Yu, ¡°Quantum Mechanical Compact Modeling of Inversion Charge in Double-Gate MOSFETs Unifying Symmetric and Asymmetric Operation Modes,¡± International Workshop on Compact Modeling, Jan. 2009, Yokohama, Japan.

Ze Yuan, Zhiping Yu, ¡°Comprehensive modeling of subthreshold swing and threshold voltage roll-off for short-channel double-gate MOSFETs¡±, International Workshop on Compact Modeling, Jan. 2010, Taipei, Taiwan

Ze Yuan, Zhidong Chen, Jinyu Zhang, Zhiping Yu, et al., ¡°Derivative of Electron Density in Non-Equilibrium Green¡¯s Function Technique and its Application to Boost Performance of Convergence,¡± Chinese Physics Letters, Vol. 26, No. 11, 2009.

Ze Yuan, Zhiping Yu, ¡°Short-Channel-Effects Modeling of DG-FETs Using Voltage-Doping Transformation Featuring FD/PD Modes,¡± Electron Device Letters, vol.30, no.11, pp.1209-1211, Nov. 2009.

Shengxi Huang, Zhe Wang, Ze Yuan, Jinyu Zhang, Zhiping Yu, ¡°Core-shell type of tunneling nanowire FETs for large driving current with unipolarity,¡± Electron Devices and Solid-State Circuits (EDSSC), 2011 International Conference of, Nov. 2011.

Personal Life

Under construction.... :(