Check the lab partners sheet for your partner assignments. If you are not listed, information is incorrect or missing, please email the TA's.
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Lab |
Description |
Due Date |
Starter Files |
Comments |
FAQ |
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Tutorial |
None |
No need to submit lab0. Use it to familiarize yourself with the FPGAs. Note: It is taken from EE183 which used a different board, but the principles remain the same. |
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Pong in MIPS code |
10/17/06 |
Quick start with XSPIM |
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MIPS and Pong on FPGA |
10/31/06 |
For the demo, use this COE file to create a bitstream. We'll test your code using it. Also, have a bitstream ready with pong code downloaded on it. |
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Pipelined MIPS |
11/14/06 |
In eeclass |
test COE file |
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Implementing your own Cache |
12/5/06 |
In eeclas |
Lab 4 testing procedure, test COE file, demo1.coe, demo2.coe (hint) |