EE108B Labs

Lab Partners

Check the lab partners sheet for your partner assignments. If you are not listed, information is incorrect or missing, please email the TA's.

Lab Equipment

Software Tools

Verilog

Tutorials

Lab Handouts

Lab

Description

Due Date

Starter Files

Comments

FAQ

Lab 0

Tutorial

None

Verilog

No need to submit lab0. Use it to familiarize yourself with the FPGAs. Note: It is taken from EE183 which used a different board, but the principles remain the same.

 

Lab 1

Pong in MIPS code

10/17/06

Starter files

Quick start with XSPIM

here

Lab 2

MIPS and Pong on FPGA

 10/31/06

Starter files

For the demo, use this COE file to create a bitstream. We'll test your code using it. Also, have a bitstream ready with pong code downloaded on it.

here

Lab 3

Pipelined MIPS

11/14/06

In eeclass

test COE file

here

Lab 4

Implementing your own Cache

12/5/06

In eeclas

Lab 4 testing procedure, test COE file, demo1.coe, demo2.coe (hint)

here

Lab Demonstration