EE180 Digital Systems Architecture

Winter 2026, Mon/Wed 3:00 PM - 4:20 PM
Location: STLC111

Instructor: Christos Kozyrakis
Teaching Assistants: Belle Angkanapiwat, Joshua Delgadillo, Sally Lee, William Zhu
Ed Discussion: Ed Stem
Staff Email: ee180-win2526-staff@lists.stanford.edu
Canvas: Canvas Home Page
Course Information: PDF

Office Hours:
Christos: Monday 4:30 PM - 5:30 PM (and by appointment). Gates 444.
Belle: Tuesdays, 10:00 AM - 12:00 PM. CoDa E401, except on 2/10: CoDa E365, 2/24: CoDa W401
Joshua: Wednesdays, 12:30 PM - 2:30 PM. CoDa E365
Sally: Mondays, 12:30 PM - 2:30 PM. Gates 415, except on 2/23: Huang Basement
William: Fridays, 10:00 AM - 12:00 PM. Gates 415, except on 1/16: Gates 498

Overview

  EE180 introduces students to computer architecture and the design of efficient computing and memory systems. The key topics of this course include: hardware/software interface (instruction set, data and thread level parallelism), assembly language programming, efficiency metrics (performance, power, energy, and cost), processor design (pipelining and vectors), memory hierarchy (cache, main memory), virtualization, basic I/O, and custom accelerator design. The programming assignments provide an introduction to performance optimization of software on a modern architecture and the design of a processor.
  At the completion of the course, you will understand how to determine the performance of processor-based digital systems, why they are designed that way, and how to implement your own accelerator design.
  EE180 is appropriate for undergraduate and graduate students who are specializing in the interrelated discipline of hardware/software systems. It is also appropriate for other EE and CS students who want to understand, optimize, or design their own processor based digital-system of any scale in their day-to-day work. Post EE180, students can take EE282, a class on advanced computer system architecture, and modern datacenter hardware/software architecture.

Schedule

Required Textbook

H&P: J. Hennessy & D. Patterson, Computer Organization & Design: The Hardware/Software Interface, 6th edition, Morgan-Kaufmann, 2020.
The book is available at the Stanford Bookstore, and one copy is on reserve at the Terman Engineering Library. The book is also available in print or digital form by online retailers.

Lectures and Assignments

DateTopicReadingsAssignments
Monday 1/5 Introduction H&P: 1.{1-5}
Wednesday 1/7 Hardware/Software Interface I H&P: 2.{1-4, 6}
Monday 1/12 Hardware/Software Interface II H&P: 2.{7-10}
Wednesday 1/14 Hardware/Software Interface III H&P: 2.{4, 11-14}
H&P: 6.3
Monday 1/19 MLK Day, No Class -
Wednesday 1/21 Efficiency Metrics H&P: 1.{6-7}
Monday 1/26 Hardware Design Overview H&P: Appendix B
Wednesday 1/28 Processor Design H&P: 4.{1-4}
Monday 2/2 Pipelined Processor I H&P: 4.{5-6}
Wednesday 2/4 Pipelined Processor II H&P: 4.7
Monday 2/9 Pipelined Processor III H&P: 4.{8-10}
Wednesday 2/11 Memory Hierarchy I H&P: 5.{1-4}
Monday 2/16 Presidents' Day, No Class -
Wednesday 2/18 Memory Hierarchy II H&P: 5.{8-10}
Monday 2/23 Memory Hierarchy III H&P: 5.10, 6.5
Wednesday 2/25 Custom Accelerators Lecture Notes
Monday 3/2 Virtual Memory H&P: 5.7
Wednesday 3/4 Operating System Support H&P: 4.9
Monday 3/9 I/O Devices & Interfaces H&P: 6.9
Wednesday 3/11 I/O Optimizations Lecture Notes
Tuesday 3/17 Final Exam (8:30AM - 11:30AM)
 

Review Sessions

The TAs will hold review sessions on most Fridays. These sessions will clarify topics covered during lecture, introduction to homework and laboratory assignments, and review special topics. Review sessions will be recorded and posted. Attendance is optional, but highly recommended.

Times: 3-4pm Friday
Location: Hewlett 102

Homework and Lab Assignments

For problem sets, we recommend working in groups of two students. A single copy of the answers should be submitted with all students' names. All problem sets are due by 11:59 PM PDT on the dates indicated on the assignment. Solutions to homework sets will be available online shortly thereafter. All assignments should be submitted through Gradescope.

For laboratory assignments, due to limited FPGA resources, we require that you work in groups of TBD for lab 2, and two students for labs 3 and 4. We recommend two students for lab 1. All lab assignments are due by 11:59 PM PDT on the dates indicated on the assignment. All lab assignments should be submitted through Gradescope.

The lab and homework release dates and due dates are in the schedule above.

Logistics

Announcements: Visit this web page regularly to access all the slides, handouts, and announcements.

Final Exam: Tuesday March 17 (3/17/25), 8:30am - 11:30am, Location : TBD.

Grading Scheme:
Homework: 10%
Lab Assignments: 35%
Midterm Exam: 15%
Final Exam: 35%
Class Participation: 5%

Collaboration: See: honor code and collaboration for some general guidelines, which apply to both project assignments and problem sets. In general, collaboration is encouraged subject to the following guidelines:

AI Policy:
We encourage the use of AI tools in the class. Examples of good uses of AI are the following: use AI for further Q&A on lecture or reading material and to help learn and use the tools needed for various assignments. We require students to report AI tool use in the class in assignments. We will also collect and share best practices in uses AI to improve learning.

We will follow guidance from the Board of Judicial Affairs regarding use of AI and the Stanford Honor Code, which notes that use of generative AI to “substantially complete” an assignment by entering the prompt and submitting the output as one’s own work is not permitted. Students should acknowledge the use of generative AI and default to disclosing such assistance when in doubt.

Adapted from a template by Andreas Viklund.