Computer Systems Laboratory Colloquium

4:15PM, Wednesday, December 5, 2001
NEC Auditorium, Gates Computer Science Building B03
For additional information consult

Computer Architecture 2000-2025
A Retrospective

Andy Glew
works for, but not representing, Intel
About the talk:

It is the year 2025. This presentation is being made to the Society of Ancient Computer Architects: a retrospective on the last quarter century of computer architecture.

This retrospective will discuss the key advances along the main-line of computer architecture, starting with out-of-order dynamic execution at the end of the 20th century, evolving through skip-ahead and implicit, speculative, multithreading to static dataflow inspired CPU microarchitectures.

This retrospective will discuss the problem of memory latency, which has been side-stepped by the dynamic execution microarchitectures, which tolerate memory latency by finding other work to do (MLP - Memory Level Parallelism). Although it is possible to "collapse" cache missing chains of pointer references for low valency data structures such as linked lists and binary trees, improving memory latency for high valency data structures such as 700-ary database B-trees and hash tables is still an unsolved problem in the year 2025.

This retrospective will briefly touch upon the maturing of the computer industry, and the resulting slowing of the pace of innovation. It will discuss the rising sawtooth wave evolutionary pattern of computer architecture, where the general upward trend in sophistication takes a backwards step whenever a new physical technology makes less sophisticated microarchitectures competitive. At the beginning of the 21st century, power, and the decline of the desktop PC form factor, introduced such a major sawtooth, as increasing wire delays did later.

This retrospective will only briefly discuss side-shows in the evolution of computer architecture, such as compute intensive (vector, DSP) workloads, and explicit parallelism.

This presentation is NOT representative of Intel, and says nothing about Intel's product plans.

About the speaker:

Andy Glew's only real claim to fame is his participation in the Intel P6 Microarchitecture 1990-1995, Intel's first dynamic execution, out-of-order, processor design.

P6 resembled the Tomasulo inspired designs Andy had been working on since before his first undergraduate computer classes at McGill University in 1980, and at the University of Illinois where he got his MS in 1991.

Andy's main contribution to Intel MMX was not burning his files when P6 decided not to do SIMD instruction set extensions. Andy held out for 64-bitness when MMX was revived a year or two later, and is responsible for placing the MMX data in the FP registers to avoid OS dependencies. Andy handed out pieces of swiss cheese at the final MMX Summit, to mark the non-orthogonality of the MMX instruction set that met the goals of minimizing instruction count.

Andy has long been involved in supporting compute intensive calculations, like MMX, dating back to his involvement with Gould vector superminicomputers. In that first job, and ever since, Andy has often been the "Computer Architect who understands OS and Software Issues", and vice versa. Andy still thinks of himself as a kernel hacker.

After P6, Andy tried to figure out what the next big thing in computer architecture is, helping found Intel Microprocessor Research Labs' CPU group in 1995-96, and a stint at the University of Wisconsin with Professor Guri Sohi 1996-2000.

Andy is notorious for his academic failures, such as failing undergraduate computer architecture twice, and not completing his Ph.D. Andy is happy that most of the projects in industry he has worked on have made billions of dollars.

Although Andy Glew has worked for Intel since 1991, this presentation is NOT representative of Intel, and says nothing about Intel's product plans.

Contact information:

Andy Glew
13131 NW Mountainview
Portland, OR 97231
work 503-264-4119, home 503-289-5451;;