The design of the clock distribution network necessary to provide a low skew and low jitter clock to the synchronous Flip-Flops and latches in all regions of the chip for a high performance microprocessor has and will continue to challenge the microprocessor circuit designer in each new generation. This talk will describe the design of Phase Locked Loop (PLL) clock generators and clock distribution networks over a number generations of microprocessors beginning with the 50MHz Intel 80486, and going through to today's 2.0 GHz Pentium 4. The network topologies enabling the design of low skew and low jitter clock networks will be presented. The talk will also describe some of the circuit design methods for low jitter analog Phase Locked Loops which have to be implemented on the same microprocessor die as the noisy high speed digital CMOS logic. A comparison of the architectural differences and skew performance achieved for clock networks in some of the industry's recent high performance microprocessors will presented. The presentation will describe some of the circuit design trends that we are likely to see as microprocessors continue grow in both transistor count and clock frequency. Since the bandwidth of the I/O circuits needed to increase after staying at 25/33MHz for a number of years, microprocessor circiut designers also started to use PLLs for the I/O clocking and are achieving up to 6.4GB/s (for 800MT/s) of I/O bandwidth today. The I/O clocking circuit's use of Phase Locked Loops will be described for two different microprocessor architectures.
Download the slides in PDF format. These slides are the final version and replace the earlier version previously posted.
About the speaker:
Ian Young was born in Melbourne, Australia. He received the B.E. and M. Eng. Science. degrees in electrical engineering from the University of Melbourne in 1972 and 1975. He received the Ph.D degree in Electrical Engineering from the University of California, Berkeley in 1978. Since 1983 he has been with the Technology Development group at Intel Corporation in Hillsboro, Oregon, where he is currently an Intel Senior Fellow and Director of Advanced Circuits and Technology Integration. He is responsible for defining and developing future circuit directions and optimizing the manufacturing process technology for high-performance microprocessor and communication products. He has served as both technical program chair and symposium chair for the IEEE/JSAP Symposium on VLSI Circuits. He was also a member of the IEEE International Solid-State Circuits Conference Technical Program Committee, serving as the Digital sub-committee chair from 1996 to 2003, and the International Technical Program Committee chair/vice-chair in 2004/2005. He has been guest editor for the Journal of Solid-State Circuits. Dr Young is an IEEE Fellow.
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