Stanford EE Computer Systems Colloquium

4:15PM, Wednesday, May 09, 2007
HP Auditorium, Gates Computer Science Building B01

Multi-core, Multiprocessor, and Memory Hierarchies:
An Application Developer's View of Next Generation Systems Enablement

Catherine H. Crawford, PhD
IBM System and Technology Group
About the talk:

Current advances in microprocessor and system technology have led to a surprising array of scale out system enablement at a commodity level driven by the inherent Moore's Law limitations of simple frequency scaling to meet performance needs. Massively multi-threaded technology, scale out clusters on commodity networks, and heterogeneous "systems on a chip" (SoC) with advanced memory hierarchy performance are currently available to a wide array of industry application developers. However, although systems are available with increasing scalability and advaced/dedicated performance components, many applications, even in technical computing, do not scale beyond 8 way for even a single ISA/Operating System architecture. Current "scalable" applications are often limited to pure distributed or "embarassingly parallel" workloads where the application is not necessarily "re-written" or re-architected for the new processors or systems, but more copies of the same executable are merely just mapped to the new numbers of threads or processors in a network. This approach in software development and applications enablement will hardly yield the performance boosts as silicon advances for a majority of applications.

In this talk, we review a history of programming paradigms along with programming models as well as discuss workloads and subsequent programming issues from current market growth segments. We combine this review of the applications and programming issues with a software view of technology and system advances to develop a sense of "whats missing" in current art for developers to engage in pragmatic parallelism in application development. Finally, an example of such enablement will be presented with the Accelerator Library Framework (ALF) and Data and Communication Synchronization (DaCS) components of the hybrid system under development with Cell Broadband Engine and x86 based environments; thus summarizing with an implementation view of how complex multi-core, multi-process, multi-ISA and memory hierarchy systems can be rendered usable by a broad audience of application developers.

About the speaker:

Catherine H. Crawford has a decade of experience in various IBM research and development teams, with deliverables ranging from low level C systems code to J2EE based applications for long term research projects as well as critical revenue stream products. She has been an architect, developer, performance analyst, and customer engagement consultant. She has led teams from 4 to 100 both in one location and globally dispersed. She is a respected industry expert in Financial Services Sector/Capital Markets Rich Media Systems and Government/Scientific Research. Currently, Cait is the Chief Architect for Next Generations Systems Software & Solutions in the Quasar Design Center, responsible for overall technical leadership for the Software Development Kit (SDK) for Cell Broadband Engine (BE) system technology. This includes Linux kernel enablement, programming model technologies (compilers, runtime, IDEs, debug tools), performance/benchmarking, optimized libraries and standards development for AMP/SoC systems. Cait graduated from the Massachusetts Institute of Technology (MIT) in 1991 with an SB in Mechanical Engineering. She completed MSE and PhD degress in Mechanical and Aerospace Engineering from Princeton University in 1994 and 1996; her research and dissertation work focused on simulation of complex turbulent flows on scale out computer architectures. She currently resides in New Hampshire with her family.

Contact information:

Catherine H. Crawford