Computer Systems Laboratory Colloquium

4:15PM, Wednesday, December 1, 1999
NEC Auditorium, Gates Computer Science Building B03

SPARC64 V: A High Performance and High Reliability 64-bit SPARC Processor

Michael C. Shebanow
HAL Computer Systems, Inc.
About the talk:
SPARC64 V is HAL's Microprocessor Division's latest generation high performance/reliability processor aimed at the high-end commercial and technical UNIX server market.

The key design goals of SPARC64 V include high expected performance relative to its competition (Ultrasparc 3/4, Itanium, HP8700, Compaq 21364, IBM Gigaprocessor), very high reliability (processor's ability to detect and recover from soft errors and other failures), and ability to perform in large-scale SMP UNIX servers (8-128 processors) with either commercial (e.g. TPC-C/D) or technical (SPEC, scientific) application workloads. With SPARC64 V, both HAL and Fujitsu have the specific goal of establishing Fujitsu as a world-wide key player in the UNIX server market.

SPARC64 V is an eight-issue superscalar, dynamically-scheduled processor employing super-speculation as a means to reduce internal execution latencies. SPARC64 V also employs a 1024-entry trace cache as a means of reducing the average pipeline length to only seven stages. For high execution performance, SPARC64 V integrates 4 integer execution units, 2 load units, 2 store units, and dual floating-point add-multiply units along with on-board 32KB and 256KB instruction caches and 8KB and 512KB data caches.

A high performance external third level cache is also supported (4MB-64MB, 16MB nominal, up to 16 GB/sec data rates), and a high speed modified UPA bus interfaces to the system (up to 8 GB/sec data rates). SPARC64 V also includes many reliability features, such as ECC on all write-back caches (internal or external), parity on internal buses, function-unit redundancy,parity/remainder checking on arithmetic operations, etc. SPARC64 V is implemented in a 0.12 micron, 6 layer copper CMOS process, and is expected to operate at 1 GHz.

About the speaker:

Michael C. Shebanow is Vice President and Chief Technical Officer at HAL Computer Systems' Microprocessor Division. He is also co-architect of the SPARC64 V processor. Michael received his Ph.D. in Computer Science from UC Berkeley in 1994.

Michael's background includes 2 1/2 years at Motorola (1989-1991) where he worked on the 88120 processor architecture, and was a member of the PowerPC architecture committee. From 1991 through 1994, he worked at HAL Computer Systems where he architected the SPARC64 I processor and managed its development. From 1994 through 1997, he worked at Cyrix Corporation on the M3 processor, both as co-architect and project manager. Michael returned to HAL in 1997.

Contact information:

Michael C. Shebanow
1315 Dell Avenue
Campbell, CA 95008
(408) 341-5237
(408) 341-5403