From pattrsn@cs.berkeley.edu Sat Jan 20 06:59:45 2007
Date: Sat, 20 Jan 2007 05:23:25 -0800
From: David Patterson <pattrsn@cs.berkeley.edu>
To: Eileen Peters Long <emp@Stanford.EDU>
Cc: Dennis Allison <allison@shasta.stanford.edu>
Subject: Re: Speak at Stanford January 17th?

Here are the revised title and abstract:

Title: "Computer Architecture is Back: The Berkeley View of  Parallel 
Computing Research Landscape "

Abstract:

The sequential processor era is now officially over, as the IT industry 
has bet its future on multiple processors per chip. The new trend is 
doubling the number of cores per chip every two years instead the 
regular doubling of uniprocessor performance. This shift toward 
increasing parallelism is not a triumphant stride forward based on 
breakthroughs in novel software and architectures for parallelism; 
instead, this plunge into parallelism is actually a retreat from even 
greater challenges that thwart efficient silicon implementation of 
traditional uniprocessor architectures.

A diverse group of University of California at Berkeley researchers from 
many backgrounds -- circuit design, computer architecture, massively 
parallel computing, computer-aided design, embedded hardware and 
software, programming languages, compilers, scientific programming, and 
numerical analysis -- met for nearly two years to discuss parallelism 
from these many angles. This talk and a technical report are the result. 
(See view.eecs.berkeley.edu)

We concluded that sneaking up on the problem of parallelism the way 
industry is planning is likely to fail, and we desperately need a new 
solution for parallel hardware and software. Here are some of our 
recommendations:

   * The overarching goal should be to make it easy to write programs
     that execute efficiently on highly parallel computing systems
   * The target should be 1000s of cores per chip, as these chips are
     built from processing elements that are the most efficient in MIPS
     (Million Instructions per Second) per watt, MIPS per area of
     silicon, and MIPS per development dollar.
   * Instead of traditional benchmarks, use 13 Dwarfs to design and
     evaluate parallel programming models and architectures. (A dwarf
     is an algorithmic method that captures a pattern of computation
     and communication.)
   * Autotuners should play a larger role than conventional compilers
     in translating parallel programs.
   * To maximize programmer productivity, future programming models
     must be more human-centric than the conventional focus on hardware
     or applications or formalisms.
   * Traditional operating systems will be deconstructed and operating
     system functionality will be orchestrated using libraries and
     virtual machines.
   * To explore the design space rapidly, use system emulators based on
     Field Programmable Gate Arrays that are highly scalable, low
     cost, and flexible. (see ramp.eecs.berkeley.edu)

Now that the IT industry is urgently facing perhaps its greatest 
challenge in 50 years, and computer architecture is a necessary but not 
sufficient component to any solution, this talk declares that computer 
architecture is interesting once again.

Eileen Peters Long wrote:
> Dave,
>
> We'll send Phil an email to see.  Do you know him? (he was at Berkeley for
> PhD)
>
> -Eileen
>
>
> On Thu, 21 Dec 2006, David Patterson wrote:
>
>   
>> Can I move the date? Looks like a conflict at Berkeley.
>> 2 weeks later would work with me. Would Philip Levis be willing to swap?
>>
>> Dave
>>
>>     
>
>