DIVISION OF ENGINEERING RESEARCH
7 March 1960
RESEARCH ON THE PHILOSOPHY OF LOGIC REALIZATION
Contract AF 33(616)6303
Copy No. 11
I INTRODUCTION (D.C.E)
The first two quarterly progress reports serve quite well to provide statements of the project's objective and early methods of approach. Before going into details of the present activities on the project, it would seem useful to run through an historical review discussion to provide overall perspective for the rest of the discussion.
We began the project with a thoroughly clear idea as to the objective we had in mind and as to the approach that we felt would be reasonable in reaching this objective. We thought that a fairly direct frontal attack would yield results relatively quickly by tearing apart a number of available schemes capable of realizing general logic, extracting the really basic features therein, and learning how to classify the resulting sets of abstracted schemes. We felt quite sure that a basic necessity for the project would be the establishment of a thorough bibliographical file which we felt would satisfy two needs in its accomplishment and possession. First, the act of establishing such a list would help us to hunt down all of the previously developed logic schemes so that the list we would have available for analysis would be essentially complete. Secondly, the possession of such a bibliographical file would undoubtedly be invaluable during the life of the project as we would almost surely have to pursue many as yet unknown problems with respect to the different schemes which we may consider. Therefore we set up, on a continuing basis, a steady portion of time for searching the literature, acquiring reprints and ASTIA documents, and filing and indexing the material. Setting up this bibliographical search was the first order of business for the project.
Then, when we started to attack the basic problem of studying the different logical schemes, we found that we needed some formalization of the description of our objects of study, so we developed the "description" outline as presented in Quarterly Progress Report 1. We also found the need for a fairly formalized stipulation of the functional requirements which a candidate scheme must fulfill in order that it be qualified for our study. This too was developed and presented in Quarterly Progress Report 1.
Our very first attempts at studying actual schemes soon raised many problems of which we had not previously been aware. Each of these problems required a certain amount of time to study and to try to determine its relationship to the overall project (see Section IIL below). Many of these problems would be quite important studies in their own right and could involve a considerable amount of work in themselves. The temptation to dive into one of these problems was resisted, principally because it seemed that none of them seemed to promise a very direct approach to the basic objective of the project.
There was therefore a period during which no great progress was made in direct analysis of logical schemes, but rather a sideways progress in finding more and more analyses which could be made. During this period the bibliographical work was continuing, however, and also, we undertook the job of isolating and tabulating all of the different schemes which had been accumulated. More details regarding the bibliographical work and the scheme tabulations are given in the first two sections of the discussion below. In December 1959, after the visit of Engelbart with Day, Krieg and Marshall at WADD, the emphasis of the project was shifted temporarily to accommodate activities associated with the forthcoming Solid States Circuit Conference which was to be held in Philadelphia, February 10, 11 and 12.
Engelbart had been asked to moderate a panel discussion at this conference on magnetic logic. Analysis of the possibilities of discussion in such a panel soon revealed the probability that the attendees at such a panel would undoubtedly not all have a background understanding in all of the different types of magnetic logic which might be involved in the discussion. It was, therefore, decided that a presentation to them in a uniform manner of the basic essentials of the different forms of magnetic logic would be very useful. It was finally realized that an oral presentation of this would require too much of the panel time and therefore we set about making a written presentation. The final form of this written survey, as distributed at the
Conference, is enclosed. This turned out to be a very good exercise for us, and we found ourselves in a position to do this quite easily since we had already accumulated the necessary bibliographical material and had it indexed in the form which allowed us easily to compile this material. We had decided anyhow that for more detailed work in scheme analyses, we would have to settle upon one particular area, and the magnetic logic area would serve quite well for this purpose. The editor of the Transaction of the PGEC has suggested that a slight expansion of this magnetic logic survey would make a very good item for him to publish. It seems worthwhile to spend some additional time, therefore, to expand this into a publishable survey which should be a useful addition to the computer literature. This seems to us to be a quite valid offshoot of the work of this project and, therefore, we intend to spend some additional time preparing the survey for publication.
Also associated with the Solid State Circuits Conference was a paper given by Engelbart on some concepts of formalized scaling considerations relative to the problem of microminiaturizing electronic systems. Initial work on this topic had been done on an SRIsponsored basis, including the writing of the summary for the conference digest. Following approval by Day, Krieg and Marshall during Engelbart's visit in December 1959, some further work has been done under this project. It has been recognized that this scaling study brings out considerations pertinent to this project, and that it seems justified to carry this work under this project enough farther to make it reasonably complete. In this respect we plan to prepare a paper for publication which carries the work as far as it seems useful under this project, and to give credit to WADD for its support of this work.
It is realized that both of the above-described efforts towards publishing papers are not in a direct line toward the objective stated for this project, and that they thus represent distractions to our main effort. It is felt, however, that both of the published items will represent quite useful contributions to the art, and both are quite useful to the project.
These different main areas of effort in which we have been involved are described below, as well as our plans for the future. The evolution of thought during the course of the project seems generally to be following a pattern. Realization of our basic objective involves concepts, relationship and problems of which we were not even aware in many cases at the outset. Also we had no procedural model to borrow from some related field of endeavor. We have had to probe and ponder a good bit just to get properly oriented, and have felt rather impatient generally with our own progress. However, we are beginning to feel as if some of the important concepts are coming into focus and that perhaps the scope of the problem and reasonable approaches to its solution are developing. More specific discussion in this regard is given below.
A. Bibliographical Work (J.L.H.)
The literature survey expended about 200-250 manhours at the research engineer level and 70 hours of secretarial help. The effort was aimed at providing a background for analyzing existing logic schemes. No attempt was made to document completely each article on every scheme variation. Rather, the file was assembled with the idea of including the first published article on any given scheme, a later more comprehensive article, and where pertinent, an article which reflected the present state of the art for that scheme. This format was not rigidly adhered to since an article could not be evaluated until it was read (or at least skimmed through). Once read, the additional effort to catalog the article (by dictating to a stenorette recorder) was negligible. The resulting file is on McBee 3 5/16" x 7 1/2" punched cards which contain the reference, (including ASTIA and SRI accession numbers for documents) and a short paragraph abstracting the article's pertinence to this specific project. (See enclosed duplicate sample.)
[the following two paragraphs are written on a punchcard and later attached to the paper
J.C.Logue, R.A.Henle, R.G.Wright, "Design and Analysis of Circuits Suitable for High Speed Computer Application," Final Report Under Contract No. AF19 (604)-1906, November 3l, 1956 through July 3l, 1957. AFCRCTR 57197, AD 133664, DE13314
The report is concerned with circuit design computation and measurements leading to the use of high frequency drift transistors in computer circuits. For maximum speed, transistors are operated out of saturation in a current mode switching technique. The work reported here seems somewhat similar to that reported by Henle in the December 1956 EJCC and by Yourke and Slobodzinski in the 1957 WJCC. This is probably worth coming back to later to see if there indeed are any new ideas in it. 21660
This card format will allow an edge-punched sorting scheme to be incorporated when the abstract framework and analysis take form.
At present, the file is divided into twenty initial categories with the following reference populations:
TABLE I. INITIAL ROUGH SCHEME CATEGORIES
Category Number of References Number of Schemes
General Survey 1 -
Vacuum Tube 6 8
Beam Switching Tubes 3 -
Transistor 40 17
Solid State Survey 2
Miscellaneous Semiconductor 5 2
Breakdowm Diodes 7 2
Magnetics Square 12
TransistorCore Loop 24 8
DiodeCore Mat'ls 27 9
All Magnetic 10 5
Ferroresonant 4 -
Parametron 8 2
Cryotron 12 2
Microwave-diode 8 4
Electroluminescent-Photoconductor 6 2
Ferroelectric 13 -
All Mechanical 1 Many
Electromechanical - -
Miscellaneous 3 -
An additional 100150 references which are not scheme descriptions but which are useful as background material, are filed by author. These are fragments of schemes such as novel amplifiers, memory techniques, multi-stable circuits, etc.
It was hoped that this survey would uncover many forgotten fragments of schemes (usually a phenomenon possessing two stable states) which would significantly aid in setting up a general model for digital logic blocks by induction. Of the schemes proposed as logic realizations, very few ideas not already known by one or more of the senior project staff were encountered.
The majority of the references are from the Proceedings of the Eastern and Western Joint Computer Conferences, the IRE Proceedings and Computer Transactions, and project reports from ASTIA,with the lastnamed being the source for roughly half the file.
The bibliographical work was useful in acquainting the junior member of the staff with the computer literature and the names of the people who have been active in the rapid development of the art. The bibliographical file has been useful as a ready reference for rough descriptions of schemes, access to the document references, and as an outline of the stateofthe art.
B. Scheme Description File (J.L.H)
The strongest use of the bibliographical file so far has been in abstracting a file of descriptions of complete, working logic schemes. The population of each category is shown in the table on page 5. This file, also on McBee punch cards, contains an engineering description of each scheme which is complete enough to state how it functions, grossly, and to identify it uniquely among similar schemes. This file is presently 61 cards and perhaps 90% complete. This work has required about 80-100 man-hours at a research and senior research engineer level.
C. Magnetic Survey (J.L.H.)
As a natural outgrowth of the bibliographical work and scheme descriptions, a survey of square loop magnetic logic schemes has been prepared. This twentypage rough draft was used as background material for a magnetic logic panel held in an evening session presided over by Engelbart at the 1960 Solid State Circuits Conference. This survey describes, in a common notation, all the magnetic schemes known to the staff, with a brief analysis of each scheme and its relation to the other schemes. A copy of this draft is enclosed. As the paper will be included in the final report and, hopefully, published in the PGEC, some rework is needed. Some of the work contemplated is penciledin on the draft copy enclosed.
About forty man-hours at the research engineer level have been exceeded on this work so far.
D. Scaling (D.C.E.)
Problems arising in the application of thin magnetic films to allmagnetic logic, under another WADD research contract over a year ago, and the initiation of a very advanced program on microminiaturization at Stanford Research Institute under
Mr. Kenneth Shoulders, both serve to simulate thinking about the effects of size scaling upon electronic components. The formalized study of scaling effects in other areas of engineering has been well worked out but isn't known by most electronic engineers. These formalized methods provide some powerful tools for studying scaling, and it seemed that they should be useful in microelectronic research.
Further work during the fall of 1959 under Stanford Research Institute sponsorship strengthened this feeling, and a paper was prepared for the 1960 Solid State Circuits Conference. The aim of the paper was primarily to carry a message that these formal methods existed and promised to be useful. The actual delivery dwelt principally on examples of scaling effects in everyday life to bring home the realization that we can't expect just to build our devices and systems smaller and find them to work the same. This conference publishes no proceedings-only a digest of 650_word summaries of each of the papers. The summary, therefore, had no room for the examples which were given orally, or for explicit discussion of how similitude theory could be useful to device and circuits men interested in microelectronics.
To make this a reasonably complete job it seems worthwhile to prepare a paper for publication now while the material is fresh in our minds, and some interest has been aroused in other minds. Some additional time to explore further the value of similitude to this project seems likewise worthwhile now, and slanting the entire paper toward our basic outlook can make its development more profitable to us. Due acknowledgment will be given to the Electronic Technology Laboratory for its support.
E. Problem Areas (D.C.E.)
In Quarterly Progress Report 2 we listed seven different problems of consideration that had been met during our studies of basic scheme characteristics. To these we have added several more:
(8) Subscheme. There can be isolated functional requirements, not sufficient to meet those of a scheme, which nonetheless will provide extremely useful functions. Many of these would need but the addition of some single device to provide a full scheme (e.g. signal regenerator, or temporary storage).
Some very important types of subscheme would be those providing the different types of large-scale storage. It is likely that any general methods developed for studying full schemes would be directly applicable to the study of subschemes as well. We think for the time being that we should concentrate on general study of full schemes but it is interesting to speculate on the possible value of this general work for special applications, especially for storage.
(9) Energy gain for fan-out. It is usually assumed that an energy (power) gain of at least two is needed for the minimal fan-out requirement (where one path branches to two). When considering lumped-device schemes, the energy (power) gain capability of each transfer cycle between elements does not have to be two, it is sufficient to be enough greater than one so that the required net gain of two can be obtained in a finite (practical) number of element-to-element transfer steps. The practical worth of this observation is not clear, but it can conceivably save a candidate scheme from being discarded too hastily someday.
(10) Bistable displacement-vs-restoring-force relationship. In informationflow paths possessing the type of multistable (we consider only bi-stable now) signal transmission characteristics that we find necessary for our schemes, there are a number of ways in which this type of characteristic is realized. In flip-flop-diodelogic schemes, the regeneratively stable characteristics of the flip-flop seem usually to provide this. With most kinds of magnetic logic, the transfer characteristics must usually provide this feature. We have experimented some with different ways to represent the relationship necessary to provide the required bistable transmission characteristics. It appears that a plot of "displacement" vs "restoring force" gives fairly uniform representations for the different schemes, and we find that the study required to isolate these variables and the effects which produce the necessary relationship between them is quite valuable in leading to better understanding of the schemes.
(11) Abstract skeletal networks. It seems apparent that, in any scheme, we shall find the transfer and manipulation of information to be associated with a physical network of signal paths, and that the signal-transmission characteristics through this network contain the essence of the capability of this scheme to realize digital logic. We know that there may well be "deadend" side branches, along a given signal flow path, which do not directly lie in the path but yet serve some necessary function to the directpath transmission. Also, some of the physical objects or phenomena associated with the signal patina are not basically necessary to the logical capability of a network. Further, some phenomena which are necessary are found inextricably (in nature) associated with some which are not necessary. We have been experimenting with network representations of different schemes in which we create different symbols for the different phenomena (even if they seem always found together, such as mmf. threshold and flux saturation in a magnetic path), and include only idealized representation of the phenomena deemed necessary to the realization of logic. We feel that this approach may turn out to provide the methodical procedure we need for attacking our basic problem. In detail, this approach is more refined than was the method used for magnetic networks on pages 8-15 of Quarterly Progress Report 1.
F. Miscellaneous. (D.C.E.)
(1) Travel and contacts. Engelbart has made two trips during the past months. The first was to the 1959 Eastern Joint Computer Conference in Boston on December 1, 2 and 3. A number of discussions relevant to this project were had. Some of the persons involved were Dr. Edmund Cohler, of Sylvania (Needham, Massachusetts), Dr. Bert Gianola, of Bell Labs, Dr. Arthur Lo, of RCA Research Labs, and Dr. Robert Minnick, of Burroughs Electrodata Division. On the way home he visited at the RCA Research Laboratories in Princeton, New Jersey, with Dr. Jan Rajchman, and with George Briggs, Les Burns, and J. T. Wallmark, and then,
of course, with Day, Krieg and Marshall at WADD.
On February 9, 1960, in Philadelphia, Engelbart attended a meeting of the IRE subcommittee 4.10 on Solid State Circuits, at which he gave a scheduled presentation of the nature, objectives and work of this project. The sub-committee holds yearly special meetings to which are invited some 60 of the country's most active men in some particular phase of solid state circuit work. The sub-committee is now planning such a meeting for next summer, and is considering topics and policies for this meeting. The Philosophy of Logic Realization presentation was well received, and is being considered as a keynote paper for the meeting to help set the general theme.
On February 10, Engelbart moderated a panel discussion on Magnetic Logic at the Solid State Circuits Conference. Over 200 persons attended and copies of the enclosed survey on Magnetic Logic were distributed. Participation on February 11 in a panel discussion on Microelectronics, and delivery on February 12 of a paper, were both associated with the scaling work mentioned above.
(2) Budget. As of February 20, some $12,638.00 remain in the project account. This is slightly less than 1/3 of the total funds with which we started the project.
III PLANS FOR THE FUTURE (D.C.E.)
We are busy now outlining a final report, in case a contract extension is not obtained, and we have to provide a report on the original schedule. This work is a very good exercise for us, and will undoubtedly benefit the project even if an extension is granted.
We plan to include in a final report (either one written soon or later) such things as an introduction to the project, bibliography and scheme listing, and treatment of the general work done to date--more or less an expansion of this report. This will represent a fair amount of work, and we are enjoying it. Expansion of the magnetic survey and the similitude works will come after the basic form of a report is well established. Then, if the extension is obtained and we have more time, we
plan to pursue item 11 in section II-E above to see how it works out as a uniform technique for analyzing schemes. It seems probable that item 10 above, and items 1 and 6 of Quarterly Progress Report 2 will usefully be involved, too. We don't know whether we will learn more by concentrating on the schemes in one phenomena field (say magnetic logic) or by concentrating on a few selected schemes from different fields-we will probably explore both possibilities a little.