Neurotrope 1


The first order of business is to find something interesting to model. We are motivated by previous experience with the silicon retina, which required thirteen different cell types, each of which had to be hardwired explicitly. Now since there are a million fibers leaving the retina through the optic tract for the brain, a structure which has on the order of a trillion neurons, each of which averages a thousand synaptic contacts, we would like to find a more efficient method for modeling this system than tracing every connection!





Now we have to abstract the rules our chip is going to compute. We are going to assert the following:

A) An active neuron (post) releases a cloud of neurotropin (blue) from its cell body.

B) A spot of light activates retinal ganglion cells (pre), which send spikes down the optic tract to growth cones at their axon terminals (AT). Active growth cones release neurotransmitter (red), exciting their target neurons. In addition, active growth cones scavenge neurotropin in their area, and are thereby able to sense the local neurotropin gradient.

C) An active growth cone migrates up the neurotropic gradient as it seeks its optimal target, which is the place that has the most neurotropin available at the instant the growth cone can sense it.

Software Simulation

Before we drop $15K+ on a chip, we want to validate the basic algorithm.

Block Diagram

block diagram

The algorithm is verified, so we can start designing the chip! Let's break the algorithm into bite-sized chunks.

Transistor Circuit


We need to draw a transistor circuit for every block in our diagram. This circuit implements all of those dark blue circles and arrows in the block diagram. Briefly, the big transistor at the bottom labeled M1 represents the charge-diffusing hexagonal lattice. The circuit in the left box handles neurotropin release by active neurons. The circuit in the right box handles neurotropin uptake by active growth cones.Ý

Circuit Simulation

We have to verify the circuits. To do this we use a program called T-Spice, which is part of the Tanner Tools design suite. T-Spice is a competent transistor simulator but it chokes on some obviously ridiculous user-designed devices like a hexagonal monolithic charge-diffusing lattice. So we can't simulate the most important feature of our design. Fortunately, we can still simulate all of the surrounding circuitry and fudge the monolithic lattice by substituting a discrete transistor network with the same topology.

This works! (I was careless and lost the proof, so you'll have to take my word for it.)



Now we translate the transistor circuits into specifications for physical devices on a silicon die. This is a screen capture from a layout design tool called L-Edit, another member of Tanner Tools. The idea is to draw colored polygons representing different layers of the fabrication process. For example, yellow represents transistors and blue represents metal. The hexagonal lattice is basically one giant transistor with a weird shape. The transparent green boxes labeled GC mark the layout corresponding to the growth cone circuits, the red box labeled N covers the neuron circuit, and the four yellow boxes cover the handshake circuits that communicate data onto and off of the chip. Physically, nodes of the lattice are about 50 microns apart. This basic cell is tiled in a larger array.

more layout

This is the full chip. The brown box in the center represents the area shown above. The chip consists of an array of hexagon cells, rimmed by communication circuits. Rows of pads on the perimeter provide space to bond metal wires onto the die for packaging.

Automatic verification of layout comprises two steps. First we need to check for design rule violations, things like wires being drawn so close that the fabrication process will accidentally short them together. We also need to check that the circuits in the layout exactly correspond to the circuits in the transistor diagrams. When everything verifies, we send the files off to MOSIS, an educational consortium in southern California, which bundles our design into a batch order for fabrication in Taiwan.

Printed Circuit Board


Fabrication and packaging takes about ten weeks. This is a good time to make the printed circuit board. We use a design program called Protel.

Chip Testing


System Integration