Publications

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2007
Njoroge, N., J. Casper, S. Wee, Y. Teslyar, D. Ge, C. Kozyrakis, and K. Olukotun, "ATLAS: a chip-multiprocessor with transactional memory support", Proceedings of the conference on Design, automation and test in Europe, San Jose, CA, USA, EDA Consortium, pp. 3–8, 2007.  Download: atlas_date_07.pdf (736.86 KB)
2011
2012
Kazandjieva, M. A., B. Heller, O. Gnawali, P. Levis, and C. Kozyrakis, "Green enterprise computing data: Assumptions and realities.", IGCC: IEEE Computer Society, pp. 1-10, 2012.  Download: paper (331.4 KB)
2013
2014
Belay, A., G. Prekas, A. Klimovic, S. Grossman, C. Kozyrakis, and E. Bugnion, "IX: A Protected Dataplane Operating System for High Throughput and Low Latency", Proceedings of the 11th USENIX Conference on Operating Systems Design and Implementation, Broomfield, CO, USA, USENIX Association, pp. 49–65, 2014.  Download: paper (309.07 KB)
Lo, D., L. Cheng, R. Govindaraju, L. A. Barroso, and C. Kozyrakis, "Towards Energy Proportionality for Large-Scale Latency-Critical Workloads", International Symposium on Computer Architecture, Minneapolis, Minnesota, 06/2014.  Download: Paper (897.16 KB); Slides (6.82 MB)
2015
Lo, D., L. Cheng, R. Govindaraju, P. Ranganathan, and C. Kozyrakis, "Heracles: Improving Resource Efficiency at Scale", International Symposium on Computer Architecture, Portland, Oregon, 06/2015.  Download: Paper (792.18 KB)
Gao, M., G. Ayers, and C. Kozyrakis, "Practical Near-Data Processing for In-memory Analytics Frameworks", International Conference on Parallel Architectures and Compilation Techniques (PACT), San Francisco, CA, 10/2015.  Download: paper (433.09 KB); slides (838.72 KB)
2016
Belay, A., G. Prekas, M. Primorac, A. Klimovic, S. Grossman, C. Kozyrakis, and E. Bugnion, "The IX Operating System: Combining Low Latency, High Throughput, and Efficiency in a Protected Dataplane", ACM Trans. Comput. Syst., vol. 34, no. 4, New York, NY, USA, ACM, pp. 11:1–11:39, 2016.  Download: 2016.ix_.tocs_.pdf (1.18 MB)
Gao, M., and C. Kozyrakis, "HRL: Efficient and Flexible Reconfigurable Logic for Near-Data Processing", 22nd IEEE Symposium on High Performance Computer Architecture (HPCA), Barcelona, Spain, 03/2016.  Download: paper (1.38 MB); slides (855.21 KB)
Gao, M., C. Delimitrou, D. Niu, K. T. Malladi, H. Zheng, B. Brennan, and C. Kozyrakis, "DRAF: A Low-Power DRAM-based Reconfigurable Acceleration Fabric", The 43rd International Symposium on Computer Architecture (ISCA), Seoul, South Korea, 06/2016.  Download: paper (1.02 MB); slides (876.98 KB)
2017
Gao, M., J. Pu, X. Yang, M. Horowitz, and C. Kozyrakis, "TETRIS: Scalable and Efficient Neural Network Acceleration with 3D Memory", The 22nd ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Xi'an, China, 04/2017.  Download: paper (1.93 MB); slides (1.06 MB)
Gao, M., C. Delimitrou, D. Niu, K. T. Malladi, H. Zheng, B. Brennan, and C. Kozyrakis, "DRAF: A Low-Power DRAM-Based Reconfigurable Acceleration Fabric", IEEE Micro Special Issue on Top Picks from the Computer Architecture Conferences, vol. 37, issue 3, 06/2017.  Download: paper (418.24 KB)