Bill Chen

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BASc, University of Toronto, Canada, 2010
MS, Stanford University, 2012
Admitted to Ph.D. Candidacy: 2010-2011

Research: Digitally Assisted, High-Speed Sampling Circuits
One of the major challenges in high-speed ADC design is maintaining a high-linearity performance across a wide band of input frequencies. This is especially true in sub-sampling ADC applications where the highest input frequency exceeds the ADC sampling clock speed and lands in higher Nyquist zones. Ample industry and military applications such as wideband spectrum analyzers, cellular base stations and radars call for ADCs operating in this regime.

The key performance limiting components in this type of spec space are the ADC input buffer and its S/H circuits, where the nonlinear input impedance looking into the S/H coupling with the nonlinear gm of the imput buffer gives rise to frequency dependent distortions. Current solutions include using a BJT buffer to boost the gm and a BJT current-mode S/H; [1] or using a modified source follower buffer with boosted voltage supplies and bootstrapped MOS switch S/H. [2] While the first solution requires a more expensive BiCMOS technology process, the second requires a lot more buffer power. In this project, we want to leverage the powerful digital linearization capabilities offered by CMOS by modeling the frequency-dependent nonlinearity in the frontend buffer and sampler and inversely correct it in the digital domain obviating the need of an expensive BiCMOS process and investing in a more power hungry input buffer. Our previous work has demonstrated this concept through modeling the simplified behavior of the NMOS switch sampler of a commercial ADC and linearizing the output in the digital domain with well-controlled foreground model calibration.

Currently, we are developing a more comprehensive nonlinearity model covering not only the switch itself but also the frontend input buffer (source follower). While the idea is viable for different speed vs linearity spec space, we focus on the design and demonstration for an ADC with SFDR > 65 ~ 70dB over an input frequency of 3GHz at the sample rate of 1.5GHz suitable for a radar application.

We automate the entire model parameter calibration process in the background by implementing an auxiliary conversion path. The auxiliary path scales down input swing to maintain good linearity at the cost of added noise. This serves as the linearity reference signal for the main path. Due to the nature of the adaptive filter, the added random noise in the auxiliary path will not affect the correction procedure.

The main ADC backend is implemented using a 4-way time-interleaved SAR ADCs where each predesigned slice is running at 400MS/s. The auxiliary ADC backend runs at half the speed of the main ADC and is implemented using a 2-way time-interleaved SAR with the same slice design.

The simulated pre- and post-linearitzation ADC SFDR sweep for input frequencies in the 3rd Nyquist zone is shown. Within the designed frequency of interest, we achieved a consistent 10 ~ 15dB SFDR improvement.


[1] R. Payne, et al. , “A 16-Bit 100 to 160 MS/s SiGe BiCMOS Pipelined ADC witch 100 dBFS SFDR,” in IEEE Journal Solid-State Circuits, Dec. 2010, pp. 2613-2622.

[2] A. Ali, et al. , “A 14b 1GS/s RF Sampling Pipelined ADC with Background Calibration,” in IEEE ISSCC Digest, Feb. 2014, section 29.3.

Email: [chenbill AT stanford DOT edu]

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