Kevin Zheng

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BSEE, Massachusetts Institute of Technology, 2012

MSEE, Massachusetts Institute of Technology, 2013

Email: kevzheng@stanford.edu

Research: Power Efficient Allocation of Analog Pre-filtering and Quantization in ADC Based High Speed Links

Modern serial link data speed has exceeded 25Gbps, and we are approaching the physical limitations of channel capacity at such high data rates for PAM2 signaling. As devices continues to scale, ADC based links gained much attention due to its ability to realize more sophicated equalization in digital domain and work with other modulation schemes such as PAM4 and duobinary to overcome current challenges. <span style="line-height: 1.5em;" />

As data rate increases to >56Gbps, the new standards call for a much lower raw BER and recommend an feedforward error correction (FEC) block in the system. The new raw BER targets tend to be in the 1e-4 to 1e-6 range. Therefore, even lower resolution ADCs (5-6 bits) can meet the system requirements. More literature has been published for power efficient ADCs at such high speeds [1]. However, there is still no definitive way in specifying such ADCs for high speed link applications since virtually all ADCs are still designed according to figure of merit (FOM).


Kevin movtiation.png

                                                                                                                                                                                   

                                                                                                                                                                                   Figure 1. Link Architecture Comparisons


My research focuses on system level analysis of ADC based links with analog pre-filtering/equalization to relax quantizer's design specification. Quantization error could be shown to have smaller effect to BER due to its bounded nature in Probability Distribution domain. Within this PDF framework, many of the ADC's non-idealities can also be considered, such as non-linearity and DNL. ADC based links open up different approaches for improving link performances, including nonlinearity cancellation and timing skew improvement with DFE coefficients. In order to avoid over-design, a full statistical analysis method has to be adopted using convolution of PDFs. An example of only uniform quantization noise and thermal noise is shown in figure 2. BER should be calculated as the tail probability of the final PDF.

Kevin pdf.PNG

                                                                                                                                                       Figure 2. Convolution of thermal noise (Gaussian) and quantization noise (uniform) PDFs


In addition, it could be shown that analog equalizer (including traditional TX FIR, CTLE and FFE) in front of the ADC could help relax the specification significantly (almost by 1 bit in figure 3). Recent publications such as [3] has shown possible power efficient implementations of analog FFEs, which enables the optimal tradeoff between AFE equalization and required ADC resolution.
Kevin tradeoff.png

                                                                                                                                                                                 Figure 3. FFE impact on ADC SQNR Performance


[1] B. Murmann, "ADC Survey" http://web.stanford.edu/~murmann/adcsurvey.html

[2] B. Murmann, “Energy limits in A/D converters,” in 2013 IEEE Faible Tension Faible Consommation, 2013, pp. 1–4.

[3] R. Boesch, K. Zheng, and B. Murmann, "A 0.003 mm2 5.2 mW/tap 20 GBd Inductor-less 5-Tap Analog RX-FFE," in Symp. VLSI Circuits Dig., Honolulu, HI, June 2016, pp. 170-171.

[4] J. Kim, E. H. Chen, J. Ren, B. S. Leibowitz, P. Satarzadeh, J. L. Zerbe, and C.-K. K. Yang, “Equalizer Design and Performance Trade-Offs in ADC-Based Serial Links,” IEEE Trans. Circuits Syst. I, vol. 58, no. 9, pp. 2096–2107, Sep. 2011.

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