Bill Chen

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BASc, University of Toronto, Canada, 2010
MS, Stanford University, 2012
Admitted to Ph.D. Candidacy: 2010-2011


Research: Digitally Assisted, High-Speed Sampling Circuits
One of the major challenges in high-speed ADC design is maintaining a high-linearity performance across a wide band of input frequencies. This is especially true in sub-sampling ADC applications where the highest input frequency exceeds the ADC sampling clock speed and lands in higher Nyquist zones. Ample industry and military applications such as wideband spectrum analyzers, cellular base stations and radars call for ADCs operating in this regime.

The key performance limiting components in this type of spec space are the ADC input buffer and its S/H circuits, where the nonlinear input impedance looking into the S/H coupling with the nonlinear gm of the imput buffer gives rise to frequency dependent distortions. Current solutions include using a BJT buffer to boost the gm and a BJT current-mode S/H; [1] or using a modified source follower buffer with boosted voltage supplies and bootstrapped MOS switch S/H. [2] While the first solution requires a more expensive BiCMOS technology process, the second requires a lot more buffer power. In this project, we want to leverage the powerful digital linearization capabilities offered by CMOS by modeling the frequency-dependent nonlinearity in the frontend buffer and sampler and inversely correct it in the digital domain obviating the need of an expensive BiCMOS process and investing in a more power hungry input buffer. Our previous work has demonstrated this concept through modeling the simplified behavior of the NMOS switch sampler of a commercial ADC and linearizing the output in the digital domain with well-controlled foreground model calibration.

Our current approach is to tape out two ADC chips. With the first chip, BLADE I, (First Silicon in July, 2015) we use the conventional ADC frontend design approach where we invest in higher power buffer and S/H to ensure sufficient linearity over wide input frequency range.


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This will serve as a benchmark comparison for our second chip, (BLADE II) where we utilize lower power ADC frontend and use digital correction to achieve high linearity. Our correction model will cover not only the non-ideal switch itself but also the distortion of frontend input buffer (source follower).


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Currently, BLADE I is in fabrication (Layout shown below) and pending for testing and measurement. BLADE II is scheduled for tapeout at the end of 2015.
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[1] R. Payne, et al. , “A 16-Bit 100 to 160 MS/s SiGe BiCMOS Pipelined ADC witch 100 dBFS SFDR,” in IEEE Journal Solid-State Circuits, Dec. 2010, pp. 2613-2622.

[2] A. Ali, et al. , “A 14b 1GS/s RF Sampling Pipelined ADC with Background Calibration,” in IEEE ISSCC Digest, Feb. 2014, section 29.3.

Email: [chenbill AT stanford DOT edu]

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