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(Created page with " Cadence Software at Stanford University Cadence University Program Member '''List of Cadence Software Available''' o Virtuoso Platform - ADE - Schematic Capture - Lay...")
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 Cadence Software at Stanford University
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Cadence Software at Stanford University  
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Cadence University Program Member
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Cadence University Program Member  
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'''List of Cadence Software Available'''
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'''List of Cadence Software Available'''  
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o Virtuoso Platform
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o Virtuoso Platform  
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- ADE
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- ADE  
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- Schematic Capture
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- Schematic Capture  
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- Layout
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- Layout  
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- Layout XL
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- Layout XL  
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- Custom Placer
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- Custom Placer  
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- Custom Router
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- Custom Router  
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- Chip Assembly Router
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- Chip Assembly Router  
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o MMSIM
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o MMSIM  
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o SoC Encounter
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o SoC Encounter  
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o Encounter Test
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o Encounter Test  
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o System-In-Package
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o System-In-Package  
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o Assura
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o Assura  
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o SPB (PCB)
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o SPB (PCB)  
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'''Research Groups Using Cadence Tools'''
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'''Research Groups Using Cadence Tools'''  
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[http://cis.stanford.edu/icl/wooley-grp/ Wooley Group]
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[http://cis.stanford.edu/icl/wooley-grp/ Wooley Group]  
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[http://vlsiweb.stanford.edu/ Horowitz Group]
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[http://vlsiweb.stanford.edu/ Horowitz Group]  
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[http://www-smirc.stanford.edu/ Tom Lee Group]
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[http://www-smirc.stanford.edu/ Tom Lee Group]  
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[http://marco.stanford.edu/swong/research.html Simon Wong Group]
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[http://marco.stanford.edu/swong/research.html Simon Wong Group]  
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[https://www.stanford.edu/group/murmann_group/cgi-bin/mediawiki/index.php/Main_Page Murmann Group]
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[https://www.stanford.edu/group/murmann_group/cgi-bin/mediawiki/index.php/Main_Page Murmann Group]  
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[http://biosystems.stanford.edu/ Ada Poon Group]
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[http://biosystems.stanford.edu/ Ada Poon Group]  
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[http://cgi.stanford.edu/~group-rsg_csl/twiki/bin/view.pl/Public/WebHome Mitra Group]
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[http://cgi.stanford.edu/~group-rsg_csl/twiki/bin/view.pl/Public/WebHome Mitra Group]  
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[[Dally Group]]
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[[Dally Group]]  
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[http://www.stanford.edu/~arbabian/Home/Welcome.html Arbabian Group]
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[http://www.stanford.edu/~arbabian/Home/Welcome.html Arbabian Group]  
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'''Courses Using Cadence Tools'''
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'''Courses Using Cadence Tools'''  
[https://ccnet.stanford.edu/ee313/ EE313 Digital MOS Integrated Circuits]  
[https://ccnet.stanford.edu/ee313/ EE313 Digital MOS Integrated Circuits]  
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[https://ccnet.stanford.edu/ee314/ EE314A RF Integrated Circuit Design]  
[https://ccnet.stanford.edu/ee314/ EE314A RF Integrated Circuit Design]  
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[https://ccnet.stanford.edu/ee314B/ EE314B Advanced RF Integrated Circuit Design]
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[https://ccnet.stanford.edu/ee314B/ EE314B Advanced RF Integrated Circuit Design]  
[https://ccnet.stanford.edu/ee371/ EE371 Advanced VLSI Circuit Design]  
[https://ccnet.stanford.edu/ee371/ EE371 Advanced VLSI Circuit Design]  
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[https://ccnet.stanford.edu/ee315a/ EE315A VLSI Signal Conditioning Circuits]  
[https://ccnet.stanford.edu/ee315a/ EE315A VLSI Signal Conditioning Circuits]  
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[https://ccnet.stanford.edu/ee315b/ EE315B VLSI Data Conversion Circuits]
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[https://ccnet.stanford.edu/ee315b/ EE315B VLSI Data Conversion Circuits]  
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[https://cadwiki.stanford.edu/mediawiki/index.php/Main_Page Cadence Tool Help at Stanford]
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[https://cadwiki.stanford.edu/mediawiki/index.php/Main_Page Cadence Tool Help at Stanford]  
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Information is provided 'as is' without warranty of any kind. No statement is made and no attempt has been made to examine the information, either with respect to operability, origin, authorship, or otherwise. Please use this information at your own risk. We recommend using it on a copy of your data to be sure you understand what it does under your conditions. Keep your master intact until you are satisfied with the use of this information within your environment.
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Information is provided 'as is' without warranty of any kind. No statement is made and no attempt has been made to examine the information, either with respect to operability, origin, authorship, or otherwise. Please use this information at your own risk. We recommend using it on a copy of your data to be sure you understand what it does under your conditions. Keep your master intact until you are satisfied with the use of this information within your environment.  
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Cadence is a registered trademark of Cadence Design Systems, Inc., 2655 Seely Avenue, San Jose, CA 95134
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Cadence is a registered trademark of Cadence Design Systems, Inc., 2655 Seely Avenue, San Jose, CA 95134  
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Last Modified: 08/02/2013
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Last Modified: 08/02/2013  
Webpage Maintained By: Man-Chia Chen (email: manchiac AT stanford DOT edu)
Webpage Maintained By: Man-Chia Chen (email: manchiac AT stanford DOT edu)

Revision as of 12:40, 23 September 2013

Cadence Software at Stanford University

Cadence University Program Member

List of Cadence Software Available

o Virtuoso Platform

- ADE

- Schematic Capture

- Layout

- Layout XL

- Custom Placer

- Custom Router

- Chip Assembly Router

o MMSIM

o SoC Encounter

o Encounter Test

o System-In-Package

o Assura

o SPB (PCB)

Research Groups Using Cadence Tools

Wooley Group

Horowitz Group

Tom Lee Group

Simon Wong Group

Murmann Group

Ada Poon Group

Mitra Group

Dally Group

Arbabian Group

Courses Using Cadence Tools

EE313 Digital MOS Integrated Circuits

EE314A RF Integrated Circuit Design

EE314B Advanced RF Integrated Circuit Design

EE371 Advanced VLSI Circuit Design

EE315A VLSI Signal Conditioning Circuits

EE315B VLSI Data Conversion Circuits

Cadence Tool Help at Stanford

Information is provided 'as is' without warranty of any kind. No statement is made and no attempt has been made to examine the information, either with respect to operability, origin, authorship, or otherwise. Please use this information at your own risk. We recommend using it on a copy of your data to be sure you understand what it does under your conditions. Keep your master intact until you are satisfied with the use of this information within your environment.

Cadence is a registered trademark of Cadence Design Systems, Inc., 2655 Seely Avenue, San Jose, CA 95134

Last Modified: 08/02/2013

Webpage Maintained By: Man-Chia Chen (email: manchiac AT stanford DOT edu)

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