`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   20:28:38 02/25/2008
// Design Name:   Timer
// Module Name:   U:/Desktop/Lab2/Lab2/timer_tb.v
// Project Name:  Lab2
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: Timer
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module timer_tb_v;

	// Inputs
	reg clk_27mhz;
	reg clk_1hz;
	reg [3:0] count_value;
	reg start_timer;

	// Outputs
	wire expired;
	wire [3:0] current_count;

	// Clock
	initial clk_27mhz <= 0;
	always #5 clk_27mhz <= !clk_27mhz;

	initial clk_1hz <= 0;
	always #500 clk_1hz <= !clk_1hz;

	// Instantiate the Unit Under Test (UUT)
	Timer uut (
		.clk_27mhz(clk_27mhz), 
		.clk_1hz(clk_1hz), 
		.count_value(count_value), 
		.start_timer(start_timer), 
		.expired(expired), 
		.current_count(current_count)
	);

	initial begin
		// Initialize Inputs
		clk_27mhz = 0;
		clk_1hz = 0;
		count_value = 5;
		start_timer = 1;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here

	end
      
endmodule

