`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   17:04:04 02/26/2008
// Design Name:   PosEdgePulse
// Module Name:   U:/Desktop/Lab2/Lab2/PosEdgePulse_tb.v
// Project Name:  Lab2
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: PosEdgePulse
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module PosEdgePulse_tb_v;

	// Inputs
	reg clk_27mhz;
	reg level_in;

	// Outputs
	wire pulse_out;

	initial clk_27mhz <= 0;
	always #5 clk_27mhz <= ~clk_27mhz;

	// Instantiate the Unit Under Test (UUT)
	PosEdgePulse uut (
		.clk_27mhz(clk_27mhz), 
		.level_in(level_in), 
		.pulse_out(pulse_out)
	);

	initial begin
		// Initialize Inputs
		clk_27mhz = 0;
		level_in = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here
		level_in = 1;

	end
      
endmodule

