`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
//	Tony Kim
//	6.111 PS2, Problem 1c
//
// Module name: counter
// Description: counter accepts a 27mhz incoming 'clock', and produces a positive
//					 pulse 'enable' for one clock period every 1 second. The internal  
//					 counter can be reset by a level input 'reset'.
//
//////////////////////////////////////////////////////////////////////////////////

module counter(clock, reset, enable);
   input clock;
   input reset;
   output enable;
	reg [24:0] q = 0;

	always @ (negedge clock)
	begin
		if(reset)
			q <= 0;
		else
			q <= q+1;
		
		// This counter counts up to 27,000,000 in hex, and then resets.
		if( q > 25'd27_000_000 ) 
			q <= 25'b0;
	end
	
	assign enable = (q == 25'd27_000_000);
	
endmodule
