library verilog;
use verilog.vl_types.all;
entity Timer is
    generic(
        TIMER_SLEEP     : integer := 0;
        TIMER_COUNT     : integer := 1
    );
    port(
        clk_27mhz       : in     vl_logic;
        clk_1hz         : in     vl_logic;
        count_value     : in     vl_logic_vector(3 downto 0);
        start_timer     : in     vl_logic;
        expired         : out    vl_logic;
        current_count   : out    vl_logic_vector(3 downto 0)
    );
end Timer;
