Switches;Very large scale integration;Asynchronous transfer mode;Pipelines;Clocks;Logic;Aggregates;Throughput;Delay;Monitoring

Pipelined multi-queue management in a VLSI ATM switch chip with credit-based flow-control
We describe the queue management block of ATLAS I, a single-chip ATM switch (roster) with optional credit-based (backpressure) flow …
G. Kornaros, Christos Kozyrakis, P. Vatsolaki, M. Katevenis
Cite DOI