EE371: Advanced VLSI Circuit Design
Spring 2006-2007

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EE371

Advanced VLSI Circuit Design

 

Class:                           Monday and Wednesday, 11:00-12:15 PM

      Location:                Gates B3

       Website:                http://eeclass.stanford.edu/ee371

      Handouts:               Available in Gates 3rd floor file cabinets or on the web

 

      Review Session:      Friday 11:00-11:50am -- Skilling 191

 

 

 

 

Instructor:                    Mark Horowitz                                        

      Telephone:              650-723-0583                                         

      Office Hours:          Monday 12:15 – 1:15; Wed 8:30-9:30

      Office                     Gates 308                                             

      E-mail:                    horowitz@stanford.edu                          

 

TAs:                             Tom Deane

      Telephone:              (during OH for SCPD students): 650-725-1765   

      Office Hours:          Tuesday 6-8pm - Packard 107

      E-mail:                    ee371ta@gmail.com                              

 

Administrator:              Teresa Lynn

      Telephone:              650-724-6540

      Office Hours:          M-F, 9-noon

      Office:                    Gates 310

      E-mail:                    tlynn@csl.stanford.edu