Links
High-Speed Signaling Chapter 19 (Sidiropoulos, Yang, Horowitz 2001)
Techniques
for high-speed implementation of NonLinear Cancellation (Kasturia Winters 91)
Wires
Line-To-Ground Capacitance Calculation (Barke 88)
Transistors
Transistor Matching (Pelgrom 89)
Transistor Matching (Lovett 98)
High-Field MOS
Model (Chen 97)
Circuits
Logical Effort Review (Harris)
Signal and Power Integrity (Lev96)
Dynamic
Logic and Latches (Gronowski96)
Clocking
Alpha Processors (Gronowski 98)
Standing Wave Clock (O’Mahony 03)
Skew Tolerant Domino (Harris97)
Latch Comparison (Stojanovic99)
Clocking Slides from EE271 (1up PDF)
Statistical Clock Skew Modeling with delay variation (Harris and Naffziger 01)
Asynchronous Sequencing
Zero Overhead Self-timing (Williams91)
Low
Power
Low Swing Core Circuits (Delganes04)
Dynamic Voltage Scaling (Burd00)
Voltage and Threshold Scaling (Gonzalez97)
Adder
Adder Slides from EE271 (1up PDF) and (2up PS)
A Taxonomy of Parallel Prefix Networks (Harris03)
Multiplier
Redundant Multiples (Bewick92)
Interconnects
Low-swing Onchip Signaling (Zhang2000)
Efficient
On-Chip Global Interconnects (RonHo2003)
CAMs
First DRAM CAM (Mundy72) (fun only to see what circuit design was like back then)
Large CAM for IP lookup (Sharfi98)
Preclassification CAM (Schultz96)
Practice Midterms: