Publications
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"Heracles: Improving Resource Efficiency at Scale",
International Symposium on Computer Architecture, Portland, Oregon, 06/2015.
Download: Paper (792.18 KB)
"Towards Energy Proportionality for Large-Scale Latency-Critical Workloads",
International Symposium on Computer Architecture, Minneapolis, Minnesota, 06/2014.
Download: Paper (897.16 KB); Slides (6.82 MB)
"Locality-aware Task Management for Unstructured Parallelism: A Quantitative Limit Study",
Proceedings of the 25th ACM Symposium on Parallelism in Algorithms and Architectures, New York, NY, USA, ACM, pp. 315–325, 2013.
Download: paper (1.52 MB)
"A case of system-level hardware/software co-design and co-verification of a commodity multi-processor system with custom hardware.",
CODES+ISSS: ACM, pp. 513-520, 2012.
Download: paper (402.69 KB)
"Hardware acceleration of transactional memory on commodity systems.",
ASPLOS: ACM, pp. 27-38, 2011.
Download: paper (1.22 MB)
"EigenBench: A Simple Exploration Tool for Orthogonal TM Characteristics",
IEEE Intl. Symposium on Workload Characterization (IISWC), Atlanta, GA, 12/2010.
Download: paper (914.55 KB)
"FARM: A Prototyping Environment for Tightly-Coupled, Heterogeneous Architectures.",
FCCM: IEEE Computer Society, pp. 221-228, 2010.
Download: paper (1.05 MB)
"Implementing and Evaluating a Model Checker for Transactional Memory Systems.",
ICECCS: IEEE Computer Society, pp. 117-126, 2010.
Download: paper (286.35 KB)
"ATLAS: a chip-multiprocessor with transactional memory support",
Proceedings of the conference on Design, automation and test in Europe, San Jose, CA, USA, EDA Consortium, pp. 3–8, 2007.
Download: atlas_date_07.pdf (736.86 KB)
"Transactional Memory Coherence and Consistency",
Proceedings of the 31st Annual International Symposium on Computer Architecture (ISCA), Munich, Germany, pp. 102–, 6/2004.